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Add global HSFLL clock control device driver #81735

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Draft for now since testing is blocked by missing firmware for the nRF54H20

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Note @ppelikan-nordic

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zephyrbot commented Nov 21, 2024

The following west manifest projects have changed revision in this Pull Request:

Name Old Revision New Revision Diff
hal_nordic zephyrproject-rtos/hal_nordic@ce87268 zephyrproject-rtos/hal_nordic#265 zephyrproject-rtos/hal_nordic#265/files

DNM label due to: 1 project with PR revision

Note: This message is automatically posted and updated by the Manifest GitHub Action.

@zephyrbot zephyrbot added manifest manifest-hal_nordic DNM This PR should not be merged (Do Not Merge) labels Nov 21, 2024
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bjarki-andreasen commented Nov 21, 2024

I need the to update the frequencies to match the opaque GDFS_FREQ_MEDHIGH in devicetree, and verify that the initial frequency of the clock is the lowest one :) Also need to find appropriate timeout for gdfs requests.

west.yml Outdated
@@ -188,7 +188,7 @@ manifest:
groups:
- hal
- name: hal_nordic
revision: 54bde38c6f6ffb3780b26ae728cf79426184384e
revision: pull/254/head

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Please change to zephyrproject-rtos/hal_nordic#261 instead, to include newest fixes.
(zephyrproject-rtos/hal_nordic#254 is closed now)

can be done by rebasing from: #81710

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Updated to use newly created PR 263 since 261 includes breaking changes to unrelated module

bjarki-andreasen and others added 8 commits November 29, 2024 17:48
Update hal_nordic revision to include nrfs services:
- GDPWR
- GDFS

Signed-off-by: Bjarki Arge Andreasen <[email protected]>
nRFs exposes now all power domains, following their actual name in the
specification. Add support for all of them in the GPD service. Note that
this is a breaking change: running this code requires a new SCFW as IDs
have changed in nRFs and so SCFW.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
Adding the implementation for the GDFS service

Signed-off-by: Paweł Pelikan <[email protected]>
Add specific device model for global hsfll clock and update dts tree
to use specific model. The clock is not fixed, and configurable at
runtime to predefined frequencies specified by the platform.

Signed-off-by: Bjarki Arge Andreasen <[email protected]>
Add device driver support for global hsfll clock.

Signed-off-by: Bjarki Arge Andreasen <[email protected]>
Extend sample to support global hsfll clock control.

Signed-off-by: Bjarki Arge Andreasen <[email protected]>
Extend test suite to test global HSFLL clock.

Signed-off-by: Bjarki Arge Andreasen <[email protected]>
Introduce feature which restricts the minimum global hsfll
frequency. This feature is selected by default to preserve the
behavior of the global hsfll before the clock control driver for
it was introduced, which configured it as a fixed clock at 320MHz.

Signed-off-by: Bjarki Arge Andreasen <[email protected]>
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5 participants