Problem Statement: To scale down the frequency of 50MHz to 3.125MHz and 195KHz and implement Pulse Width Modulation on it. designing a Frequency Scaling and Pulse Width Modulation block which has a 50MHz clock and 4-bit Duty cycle as inputs. outputs which can generate a variable duty cycle pulse width modulated signal with frequency of 195KHz and 3125KHz clock signal.
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AbijithT2003/verilog-using-intel-quarts
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solution to problem statement on frequency scaling and Pulse Width Modulation on VERILOG(INTEL QUARTZ)
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