Merge remote-tracking branch 'origin/master' into anton/frep

CHANGELOG.md

@@ -1,8 +1,7 @@
 # Changelog
 
-## Upcoming
+## 2.2.3
 
- - Feature: Added `Xfrep` extension for the snitch emulator getting us closer to full snitch emulation
  - Feature: Adding support for 64 bit floating point operations
  - BugFix: Fix `__all__` to now properly work (use name strings instead of values)
 

riscemu/core/registers.py

@@ -9,7 +9,7 @@
 
 from ..helpers import *
 
-from . import Int32, BaseFloat, Float32, Float64
+from . import Int32, BaseFloat
 
 
 class Registers:
@@ -223,7 +223,7 @@ def get_f(self, reg: str) -> BaseFloat:
             raise RuntimeError("Invalid float register: {}".format(reg))
         return self.float_vals[reg]
 
-    def set_f(self, reg: str, val: Union[float, BaseFloat]):
+    def set_f(self, reg: str, val: BaseFloat):
         if not self.infinite_regs and reg not in self.float_regs:
             raise RuntimeError("Invalid float register: {}".format(reg))
         self.float_vals[reg] = self._float_type.bitcast(val)

riscemu/riscemu_main.py

@@ -12,6 +12,7 @@
 from .config import RunConfig
 from .helpers import FMT_GRAY, FMT_NONE
 from .parser import AssemblyFileLoader
+from .instructions.float_base import FloatArithBase
 
 
 @dataclass
@@ -193,7 +194,12 @@ def parse_argv(self, argv: List[str]):
             if selected
         )
 
-        # if use_libc is given, attach libc to path
+        # remove floating point isas if they do not meet the flen requirements
+        for isa in tuple(self.selected_ins_sets):
+            if issubclass(isa, FloatArithBase) and isa.flen > args.flen:
+                self.selected_ins_sets.remove(isa)
+
+        # if "use_libc" is given, attach libc to path
         if self.cfg.use_libc:
             self.add_libc_to_input_files()