adding tests, fixing bugs

riscemu/core/usermode_cpu.py

@@ -64,9 +64,7 @@ def step(self, verbose: bool = False):
             self.cycle += 1
             ins = self.mmu.read_ins(self.pc)
             if verbose:
-                print(
-                    FMT_CPU + "   Running 0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins)
-                )
+                print(FMT_CPU + "   0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins))
             self.pc += self.INS_XLEN
             self.run_instruction(ins)
         except RiscemuBaseException as ex:

snitch/__main__.py

@@ -8,18 +8,20 @@
 import sys
 
 from .regs import StreamingRegs
-from .xssr import RV32_Xssr_pseudo
+from .xssr import Xssr_pseudo
+from .frep import FrepEnabledCpu, Xfrep
 from riscemu.riscemu_main import RiscemuMain
 
 
 class SnitchMain(RiscemuMain):
-    def configure_cpu(self):
-        super().configure_cpu()
+    def instantiate_cpu(self):
+        self.cpu = FrepEnabledCpu(self.selected_ins_sets, self.cfg)
         self.cpu.regs = StreamingRegs(self.cpu.mmu)
+        self.configure_cpu()
 
     def register_all_isas(self):
         super().register_all_isas()
-        self.available_ins_sets.update({"Xssr": RV32_Xssr_pseudo})
+        self.available_ins_sets.update({"Xssr": Xssr_pseudo, "Xfrep": Xfrep})
 
 
 if __name__ == "__main__":

snitch/frep.py

@@ -1,5 +1,6 @@
 from typing import List, Type, Union, Set, Literal
 
+from riscemu.colors import FMT_CPU, FMT_NONE
 from riscemu.config import RunConfig
 from riscemu.core import UserModeCPU
 from riscemu.instructions import InstructionSet, Instruction, RV32F
@@ -27,7 +28,8 @@ def __init__(self, instruction_sets: List[Type["InstructionSet"]], conf: RunConf
 
     def step(self, verbose: bool = False):
         if self.repeats is None:
-            super().step()
+            super().step(verbose=verbose)
+            return
         # get the spec
         spec: FrepState = self.repeats
         self.repeats = None
@@ -37,6 +39,22 @@ def step(self, verbose: bool = False):
             for i in range(spec.ins_count)
         ]
 
+        if verbose:
+            print(
+                FMT_CPU
+                + "┌────── floating point repetition ({}) {} times".format(
+                    spec.mode, spec.rep_count + 1
+                )
+            )
+            for i, ins in enumerate(instructions):
+                print(
+                    FMT_CPU
+                    + "│  0x{:08X}:{} {}".format(
+                        self.pc + i * self.INS_XLEN, FMT_NONE, ins
+                    )
+                )
+            print(FMT_CPU + "└────── end of floating point repetition" + FMT_NONE)
+
         pc = self.pc
         if spec.mode == "outer":
             for _ in range(spec.rep_count + 1):
@@ -46,6 +64,8 @@ def step(self, verbose: bool = False):
             for ins in instructions:
                 for _ in range(spec.rep_count + 1):
                     self.run_instruction(ins)
+        else:
+            raise RuntimeError(f"Unknown frep mode: {spec.mode}")
 
         self.pc = pc + (spec.ins_count * self.INS_XLEN)
 

snitch/regs.py

@@ -76,9 +76,6 @@ def get_f(self, reg, mark_read=True) -> "Float32":
         addr = stream.base + (stream.pos * stream.stride)
         val = self.mem.read_float(addr)
         # increment pos
-        print(
-            "stream: got val {} from addr 0x{:x}, stream {}".format(val, addr, stream)
-        )
         stream.pos += 1
         return val
 
@@ -92,8 +89,5 @@ def set_f(self, reg, val: "Float32", mark_set=True) -> bool:
         addr = stream.base + (stream.pos * stream.stride)
         self.mem.write(addr, 4, bytearray(val.bytes))
 
-        print(
-            "stream: wrote val {} into addr 0x{:x}, stream {}".format(val, addr, stream)
-        )
         stream.pos += 1
         return True

snitch/xssr.py

@@ -3,7 +3,7 @@
 from .regs import StreamingRegs, StreamDef, StreamMode
 
 
-class RV32_Xssr_pseudo(InstructionSet):
+class Xssr_pseudo(InstructionSet):
     def instruction_ssr_enable(self, ins: Instruction):
         self._stream.enabled = True
 

test/filecheck/snitch/frep_only.asm

@@ -0,0 +1,17 @@
+.text
+.globl main
+main:
+        li          t0, 0
+        fcvt.s.w    ft0, t0
+        li          t0, 1
+        fcvt.s.w    ft1, t0
+
+        printf      "ft0 = {}, ft1 = {}", ft0, ft1
+        // repeat 100 times
+        li          t0, 99
+        frep.i      t0, 1, 0, 0
+        fadd.s      ft0, ft0, ft1   // add one
+        printf      "100 * 1 = {}", ft1
+
+        li          a0, 0
+        ret

test/filecheck/snitch/xssr_only.asm

@@ -0,0 +1,69 @@
+// RUN: python3 -m snitch %s -o libc | filecheck %s
+
+.data
+
+vec0:
+.word 0x0, 0x3f800000, 0x40000000, 0x40400000, 0x40800000, 0x40a00000, 0x40c00000, 0x40e00000, 0x41000000, 0x41100000
+vec1:
+.word 0x0, 0x3f800000, 0x40000000, 0x40400000, 0x40800000, 0x40a00000, 0x40c00000, 0x40e00000, 0x41000000, 0x41100000
+dest:
+.space 40
+
+.text
+.globl main
+
+main:
+    // ssr config
+    ssr.configure   0, 10, 4
+    ssr.configure   1, 10, 4
+    ssr.configure   2, 10, 4
+
+    la              a0, vec0
+    ssr.read        a0, 0, 0
+
+    la              a0, vec1
+    ssr.read        a0, 1, 0
+
+    la              a0, dest
+    ssr.write       a0, 2, 0
+
+    ssr.enable
+
+    // set up loop
+    li a0, 10
+loop:
+    fadd.s      ft2, ft0, ft1
+
+    addi a0, a0, -1
+    bne  a0, zero, loop
+
+    // end of loop:
+    ssr.disable
+
+    // check values were written correctly:
+    la t0, vec0
+    la t1, vec1
+    li a0, 40
+loop2:
+    add     s0, t0, a0
+    add     s1, t1, a0
+    // load vec0 element
+    flw     ft0, 0(s0)
+    // load vec1 element
+    flw     ft1, 0(s1)
+    // assert ft1 - ft0 == ft0
+    fsub.s  ft2, ft1, ft0
+    feq.s   s0, ft2, ft0
+    beq     zero, s0, fail
+
+    addi a0, a0, -4
+    bne  a0, zero, loop2
+
+    ret
+
+fail:
+    printf "failed {} != {} (at {})", ft0, ft1, a0
+    li a0, -1
+    ret
+
+// CHECK: [CPU] Program exited with code 0