a bunch of fixes

CHANGELOG.md

@@ -1,5 +1,12 @@
 # Changelog
 
+## Upcoming
+
+- BugFix: Fix `malloc` implementation from being just wrong to being right (I think?)
+- BugFix: Fix `MMU.translate_address` to actually return the best match (wow!)
+- Feature: The instruction trace now contains register and symbol values starting at verbosity level 3
+- BugFix: RVDebug got better at finding out if a float or int register was meant
+
 ## 2.2.6
 
  - Feature: Canonicalize register names when parsing, converting e.g. `x0 -> zero` or `fp -> s0`.

riscemu/core/mmu.py

@@ -250,7 +250,7 @@ def key(x):
         best = ("", float("inf"))
         for name, val in best_fit:
             if address - val < best[1]:
-                best = (name, val)
+                best = (name, address - val)
             if address - val == best[1]:
                 if best[0] in elf_markers:
                     best = (name, val)
@@ -264,10 +264,11 @@ def key(x):
                 sec.owner, sec.name, address - sec.base, address
             )
 
-        return str(
-            "{}:{} at {} (0x{:0x}) + 0x{:0x}".format(
-                sec.owner, sec.name, name, val, address - val
-            )
+        if val == 0:
+            return "{}:{} {}".format(sec.owner, sec.name, name)
+
+        return "{}:{} at {} (0x{:0x}) + 0x{:0x}".format(
+            sec.owner, sec.name, name, address + val, val
         )
 
     def has_continuous_free_region(self, start: int, end: int) -> bool:

riscemu/core/usermode_cpu.py

@@ -10,7 +10,7 @@
 from typing import List, Type
 
 from ..config import RunConfig
-from ..colors import FMT_CPU, FMT_NONE, FMT_ERROR
+from ..colors import FMT_CPU, FMT_NONE, FMT_ERROR, FMT_GRAY, FMT_CYAN
 from ..debug import launch_debug_session
 from ..syscall import SyscallInterface, get_syscall_symbols
 from . import (
@@ -21,6 +21,8 @@
     RiscemuBaseException,
     LaunchDebuggerException,
     PrivModes,
+    Instruction,
+    SimpleInstruction,
 )
 
 if typing.TYPE_CHECKING:
@@ -64,7 +66,11 @@ def step(self, verbose: bool = False):
             self.cycle += 1
             ins = self.mmu.read_ins(self.pc)
             if verbose:
-                print(FMT_CPU + "   0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins))
+                if self.conf.verbosity > 2:
+                    ins_str = self._format_ins(ins)
+                else:
+                    ins_str = str(ins)
+                print(FMT_CPU + "   0x{:08X}:{} {}".format(self.pc, FMT_NONE, ins_str))
             self.pc += self.INS_XLEN
             self.run_instruction(ins)
         except RiscemuBaseException as ex:
@@ -125,3 +131,22 @@ def setup_stack(self, stack_size: int = 1024 * 4) -> bool:
             )
 
         return True
+
+    def _format_arg(self, arg: str, ins: Instruction) -> str:
+        if arg in self.regs.vals or arg in self.regs.valid_regs:
+            return "{}{}=0x{:x}{}".format(
+                arg, FMT_GRAY, self.regs.get(arg, False), FMT_NONE
+            )
+        elif arg in self.regs.float_vals or arg in self.regs.float_regs:
+            return "{}{}={}{}".format(arg, FMT_GRAY, self.regs.get_f(arg), FMT_NONE)
+        elif isinstance(ins, SimpleInstruction):
+            val = ins.context.resolve_label(arg)
+            if val is None:
+                val = ins.context.resolve_numerical_label(arg, ins.addr)
+            if val is None:
+                return FMT_CYAN + arg + FMT_NONE
+            return "{}{}=0x{:x}{}".format(arg, FMT_GRAY, val, FMT_NONE)
+
+    def _format_ins(self, ins: Instruction) -> str:
+        args = ", ".join(self._format_arg(arg, ins) for arg in ins.args)
+        return "{}\t{}".format(ins.name, args)

riscemu/instructions/RV_Debug.py

@@ -53,6 +53,6 @@ def instruction_print_uhex(self, ins: Instruction):
         )
 
     def smart_get_reg(self, reg_name: str) -> Union[Int32, BaseFloat]:
-        if reg_name[0] == "f":
+        if reg_name[0] == "f" or reg_name in self.regs.float_vals:
             return self.regs.get_f(reg_name)
         return self.regs.get(reg_name)

riscemu/libc/stdlib.s

@@ -33,15 +33,15 @@ _malloc_base_ptr:
 malloc:
         // set aside size in s0
         sw  s0, -4(sp)
-        mv  a0, s0
+        mv  s0, a0
         la  t0, _malloc_base_ptr
         lw  t1, 0(t0)
         beq t1, zero, _malloc_init
 _malloc_post_init:
         // if we are here, we always have
         // t0 = (&_malloc_base_ptr)
         // t1 = *(&_malloc_base_ptr)
-        // new we load
+        // now we load
         // t2 = base_ptr_offset
         lw  t2, 4(t0)
         // add allocated size to offset
@@ -66,12 +66,11 @@ _malloc_init:
         li  a7, SCALL_MMAP2
         ecall           // invoke syscall
         // check for error code
-        li  t0, -1
-        beq a0, t0, _malloc_fail
+        li  t2, -1
+        beq a0, t2, _malloc_fail
         // if succeeded, load &_malloc_base_ptr
-        la  t0, _malloc_base_ptr
         // put value of _malloc_base_ptr into t1
-        mv  a0, t1
+        mv  t1, a0
         // save base ptr to _malloc_base_ptr
         sw  t1, 0(t0)
         // jump to post_init