TwoStage OpAmp gets some built-in knowledge. Its not working great yet?

AutoCkt/Server/autockt_server/opamps/TwoStageOpAmp.py

@@ -17,44 +17,44 @@
 def TwoStageOpAmp(p: Params) -> h.Module:
     """# Two Stage OpAmp"""
 
+    # FIXME: move to testbench(?)
     cl = h.prefix.Prefixed(number=1e-11)
 
+    # Multiplier functions of the parametric devices
+    nbias = lambda x: nmos(m=p.nbias * x)
+    ninp = lambda x: nmos(m=p.ninp * x)
+    pmoses = lambda x: pmos(m=p.pmoses * x)
+
     @h.module
     class TwoStageOpAmp:
-
         # IO Interface
         VDD, VSS = 2 * h.Input()
         ibias = h.Input()
-
         inp = h.Diff(desc="Differential Input", port=True, role=h.Diff.Roles.SINK)
         out = h.Output()
 
-        # Internal Signals
-        net3, net4, net5 = h.Signals(3)
+        # Implementation
+        out1 = h.Diff()
+
+        # Input Bias
+        mn4 = nbias(x=1)(d=ibias, g=ibias, s=VSS, b=VSS)
+        mn3 = nbias(x=2 * p.alpha)(g=ibias, s=VSS, b=VSS)
+
+        # Input Pair
+        minp = h.Pair(ninp(x=p.alpha))(d=out1, g=inp, s=mn3.d, b=VSS)
 
-        # Input Stage
-        mp1 = pmos(m=p.mp1)(
-            d=net4, g=net4, s=VDD, b=VDD
-        )  # Current mirror within the input stage
-        mp2 = pmos(m=p.mp1)(
-            d=net5, g=net4, s=VDD, b=VDD
-        )  # Current mirror within the input stage
-        mn1 = nmos(m=p.mn1)(d=net4, g=inp.n, s=net3, b=net3)  # Input MOS pair
-        mn2 = nmos(m=p.mn1)(d=net5, g=inp.p, s=net3, b=net3)  # Input MOS pair
-        mn3 = nmos(m=p.mn3)(d=net3, g=ibias, s=VSS, b=VSS)  # Mirrored current source
+        # Input Stage Load
+        mpld = h.Pair(pmoses(x=p.alpha))(d=out1, g=out1.n, s=VDD, b=VDD)
 
         # Output Stage
-        mp3 = pmos(m=p.mp3)(d=out, g=net5, s=VDD, b=VDD)  # Output inverter
-        mn5 = nmos(m=p.mn5)(d=out, g=ibias, s=VSS, b=VSS)  # Output inverter
-        CL = h.Cap(c=cl)(p=out, n=VSS)  # Load capacitance
+        mp3 = pmoses(x=p.beta)(d=out, g=out1.p, s=VDD, b=VDD)
+        mn5 = nbias(x=p.beta)(d=out, g=ibias, s=VSS, b=VSS)
 
-        # Biasing
-        mn4 = nmos(m=p.mn4)(
-            d=ibias, g=ibias, s=VSS, b=VSS
-        )  # Current mirror co-operating with mn3
+        # Load capacitance... FIXME what do we do with ya
+        CL = h.Cap(c=cl)(p=out, n=VSS)
 
-        # Compensation Network
-        Cc = h.Cap(c=p.cc)(p=net5, n=out)  # Miller Capacitance
+        # Miller Compensation Cap
+        cc = h.Cap(c=p.cc)(p=out1.p, n=out)
 
     return TwoStageOpAmp
 

AutoCkt/Server/autockt_server/opamps/tb.py

@@ -26,16 +26,15 @@ class OpAmpTb:
         VSS = h.Port()  # The testbench interface: sole port VSS
 
         # Drive VDD
-        vdc = h.Vdc(dc=params.VDD)(n=VSS)
+        VDD, sig_out, ibias = 3 * h.Signal()
+        vdc = h.Vdc(dc=params.VDD)(p=VDD, n=VSS)
         inp = h.Diff()
-        sig_out = h.Signal()
-        ibias = h.Signal()
         sig_p = h.Vdc(dc=vicm, ac=+0.5)(p=inp.p, n=VSS)
         sig_n = h.Vdc(dc=vicm, ac=-0.5)(p=inp.n, n=VSS)
-        Isource = h.Isrc(dc=params.ibias)(p=vdc.p, n=ibias)
+        Isource = h.Isrc(dc=params.ibias)(p=VSS, n=ibias)
 
         # The Op-Amp DUT
-        inst = params.dut(VDD=vdc.p, VSS=VSS, ibias=ibias, inp=inp, out=sig_out)
+        inst = params.dut(VDD=VDD, VSS=VSS, ibias=ibias, inp=inp, out=sig_out)
 
     return OpAmpTb
 

AutoCkt/Shared/autockt_shared/opamp.py

@@ -11,61 +11,40 @@
 from .typing import as_param_specs, as_target_specs
 
 
+def intparam(desc: str, default: int = 4) -> Field:
+    """# Positive integer-valued parameter"""
+    return Field(
+        description=desc,
+        default=default,
+        ge=1,
+        le=100,
+        step=1,
+    )
+
+
 @dataclass
 class OpAmpInput:
     """
     Input type for AutoCkt library, a state of result
     """
 
-    mp1: int = Field(
-        description="number of units of specific pmos transistor",
-        default=34,
-        ge=1,
-        le=100,
-        step=1,
-    )
-    mn1: int = Field(
-        description="number of units of specific nmos transistor",
-        default=34,
-        ge=1,
-        le=100,
-        step=1,
-    )
-    mp3: int = Field(
-        description="number of units of specific pmos transistor",
-        default=34,
-        ge=1,
-        le=100,
-        step=1,
-    )
-    mn3: int = Field(
-        description="number of units of specific nmos transistor",
-        default=34,
-        ge=1,
-        le=100,
-        step=1,
-    )
-    mn4: int = Field(
-        description="number of units of specific nmos transistor",
-        default=34,
-        ge=1,
-        le=100,
-        step=1,
-    )
-    mn5: int = Field(
-        description="number of units of specific nmos transistor",
-        default=15,
-        ge=1,
-        le=100,
-        step=1,
+    # Unit device sizes
+    nbias: int = intparam("Bias Nmos Unit Width", 2)
+    ninp: int = intparam("Input Nmos Unit Width", 2)
+    pmoses: int = intparam("Pmos Unit Width", 2)
+
+    # Current Mirror Ratios
+    alpha: int = intparam("Alpha (Input) Current Ratio", 40)
+    beta: int = intparam("Beta (Output) Current Ratio", 40)
+
+    # Other
+    cc: int = Field(
+        description="Compensation Cap Value (fF)",
+        default=1000,
+        ge=10,
+        le=10_000,
+        step=10,
     )
-    cc: float = Field(
-        description="capacitance of specific capacitor",
-        default=2.1e-12,
-        ge=0.1e-12,
-        le=10.0e-12,
-        step=0.1e-12,
-    )  # Or maybe `str`, or the Hdl21/ VLSIR `Prefixed` fixed-point type
 
 
 @dataclass