[uvmgen] compile pass

Dragon-Git · Nov 19, 2023 · b1dbdfe · b1dbdfe
1 parent f55da32
commit b1dbdfe
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Showing 7 changed files with 50 additions and 53 deletions.
diff --git a/.vscode/systemverilog.code-snippets b/.vscode/systemverilog.code-snippets
@@ -318,10 +318,10 @@
 	"UVM wait and get config": {
 		"prefix": "p-wait_get_cfg",
 		"body": [
-		  "    always begin",
-		  "      uvm_config_db#(int)::wait_modified(null, \"*\",\"${1:mycfg}\");",
-		  "      void'(uvm_config_db#(int)::get(null, \"${1}\",\"${1}\"));",
-		  "    end"
+		  "always begin",
+		  "  uvm_config_db#(int)::wait_modified(null, \"*\", \"${1:mycfg}\");",
+		  "  void'(uvm_config_db#(int)::get(null, \"\", \"${1}\", ${1}));",
+		  "end"
 		],
 		"description": "UVM wait modified then get config"
 	},

diff --git a/src/uvmgen/templates/agt_pkg/agt.mako.sv b/src/uvmgen/templates/agt_pkg/agt.mako.sv
@@ -55,8 +55,8 @@ class ${agent_name}_agt extends uvm_agent;
         if (!uvm_config_db#(vif)::get(this, "", "if", agt_if)) begin
            `uvm_fatal("AGT/NOVIF", "No virtual interface specified for this agent instance")
         end
-        uvm_config_db# (vif)::set(this,"drv","vif",drv.drv_if);
-        uvm_config_db# (vif)::set(this,"mon","vif",mon.mon_if);
+        uvm_config_db# (vif)::set(this,"drv","drv_if", agt_if);
+        uvm_config_db# (vif)::set(this,"mon","mon_if", agt_if);
     endfunction: build_phase
 
     virtual function void connect_phase(uvm_phase phase);

diff --git a/src/uvmgen/templates/agt_pkg/mon.mako.sv b/src/uvmgen/templates/agt_pkg/mon.mako.sv
@@ -135,21 +135,18 @@ task ${agent_name}_mon::tx_monitor();
       ${agent_name}_item tr;
       // ToDo: Wait for start of transaction
 
-      `uvm_do_callbacks(${agent_name}_mon,${agent_name}_mon_callbacks,
-                    pre_trans(this, tr))
+      `uvm_do_callbacks(${agent_name}_mon,${agent_name}_mon_callbacks, pre_trans(this, tr))
       `uvm_info("TX_MONITOR", "Starting transaction...",UVM_LOW)
       // ToDo: Observe first half of transaction
 
       // ToDo: User need to add monitoring logic and remove $finish
       `uvm_info("TX_MONITOR"," User need to add monitoring logic ",UVM_LOW)
-	  $finish;
-      `uvm_do_callbacks(${agent_name}_mon,${agent_name}_mon_callbacks,
-                    pre_ack(this, tr))
+	   // $finish;
+      `uvm_do_callbacks(${agent_name}_mon,${agent_name}_mon_callbacks, pre_ack(this, tr))
       // ToDo: React to observed transaction with ACK/NAK
       `uvm_info("TX_MONITOR", "Completed transaction...",UVM_HIGH)
       `uvm_info("TX_MONITOR", tr.sprint(),UVM_HIGH)
-      `uvm_do_callbacks(${agent_name}_mon,${agent_name}_mon_callbacks,
-                    post_trans(this, tr))
+      `uvm_do_callbacks(${agent_name}_mon,${agent_name}_mon_callbacks, post_trans(this, tr))
 % if (mon2cov_con_approach == "analysis_port") :
       mon_analysis_port.write(tr);
 % endif

diff --git a/src/uvmgen/templates/env_pkg/env.mako.sv b/src/uvmgen/templates/env_pkg/env.mako.sv
@@ -14,6 +14,7 @@ class ${env_name} extends uvm_env;
    // Declear agent
 % for child_type, child_name in env_childs.items():
    ${child_type} ${child_name};
+   ${child_type[:-3]}cfg ${child_name[:-3]}cfg;
 % endfor
 
    `uvm_component_utils(${env_name})
@@ -37,7 +38,10 @@ endfunction:new
 function void ${env_name}::build_phase(uvm_phase phase);
    super.build();
 % for child_type, child_name in env_childs.items():
-   ${child_name} = ${child_type}::type_id::create("${child_name}",this); 
+   ${child_name} = ${child_type}::type_id::create("${child_name}",this);
+   ${child_name[:-3]}cfg = ${child_type[:-3]}cfg::type_id::create("${child_name[:-3]}cfg",this);
+   uvm_config_db#(${child_type[:-3]}cfg)::set(this, "${child_name}", "cfg", ${child_name[:-3]}cfg);
+
 % endfor
 
    //ToDo: Instantiate other components,callbacks and TLM ports if added by user  

diff --git a/src/uvmgen/templates/tb_lib/filelist.f b/src/uvmgen/templates/tb_lib/filelist.f
@@ -1,15 +1,11 @@
-+incdir+$TB_DIR/spi_agt_pkg
-$TB_DIR/spi_agt_pkg/spi_if.gen.sv
-$TB_DIR/spi_agt_pkg/spi_agt_pkg.gen.sv
-
-+incdir+$TB_DIR/spi_env_pkg
-$TB_DIR/spi_env_pkg/spi_env_pkg.gen.sv
-
-+incdir+$TB_DIR/spi_seq_lib_pkg
-$TB_DIR/spi_seq_lib_pkg/spi_seq_lib_pkg.gen.sv
-
-+incdir+$TB_DIR/spi_test_pkg
-$TB_DIR/spi_test_pkg/spi_test_pkg.gen.sv
-
-+incdir+$TB_DIR/tb_lib
-// $TB_DIR/tb_pkg/tb.sv
+% for pkg in filelist_pkgs:
+    % if "agt" in pkg:
+$TB_DIR/${pkg}/${pkg.replace("agt_pkg", "if")}.gen.sv
+    % endif
++incdir+$TB_DIR/${pkg}
+    % if "tb" not in pkg:
+$TB_DIR/${pkg}/${pkg}.gen.sv
+    % else:
+$TB_DIR/${pkg}/tb.gen.sv
+    % endif
+% endfor
diff --git a/src/uvmgen/templates/tb_lib/tb.mako.sv b/src/uvmgen/templates/tb_lib/tb.mako.sv
@@ -4,37 +4,34 @@
 module tb();
     import uvm_pkg::*;
     `include "uvm_macros.svh"
-    import ${test_pkg_name}_pkg::*;
+% for pkg in import_pkgs:
+    import ${pkg}::*;
+% endfor
 
-    reg[7:0] rxd;
-    reg rx_dv;
-    wire[7:0] txd;
-    wire tx_en;
-
-    my_if input_if(clk, rst_n);
-    my_if output_if(clk, rst_n);
-
-    bus_if b_if(clk, rst_n);
+    typedef virtual ${if_name} vif;
+    ${if_name} mst_if(clk, rst_n);
+    ${if_name} slv_if(clk, rst_n);
+    ${if_name} ctrl_if(clk, rst_n);
 
     // ToDo: Include Dut instance here
-    dut my_dut(.clk          (clk               ),
-           .rst_n        (rst_n             ),
-           .bus_cmd_valid(b_if.bus_cmd_valid), 
-           .bus_op       (b_if.bus_op       ), 
-           .bus_addr     (b_if.bus_addr     ), 
-           .bus_wr_data  (b_if.bus_wr_data  ), 
-           .bus_rd_data  (b_if.bus_rd_data  ), 
-           .rxd          (input_if.data     ),
-           .rx_dv        (input_if.valid    ),
-           .txd          (output_if.data    ),
-           .tx_en        (output_if.valid   ));
+    // dut my_dut(.clk          (clk               ),
+    //        .rst_n        (rst_n             ),
+    //        .bus_cmd_valid(b_if.bus_cmd_valid), 
+    //        .bus_op       (b_if.bus_op       ), 
+    //        .bus_addr     (b_if.bus_addr     ), 
+    //        .bus_wr_data  (b_if.bus_wr_data  ), 
+    //        .bus_rd_data  (b_if.bus_rd_data  ), 
+    //        .rxd          (input_if.data     ),
+    //        .rx_dv        (input_if.valid    ),
+    //        .txd          (output_if.data    ),
+    //        .tx_en        (output_if.valid   ));
 
     // Clock Generation
     int period = 10;
     logic clk = 1'b0;
     always begin
       uvm_config_db#(int)::wait_modified(null, "*","period");
-      void'(uvm_config_db#(int)::get(null, "period","period"));
+      void'(uvm_config_db#(int)::get(null, "", "period", period));
     end
     always #(period/2) clk = ~clk;
 
@@ -43,11 +40,12 @@ module tb();
     logic rst_n = 1'b0;
     always begin
       uvm_config_db#(int)::wait_modified(null, "*","rst_delay");
-      void'(uvm_config_db#(int)::get(null, "rst_delay","rst_delay"));
+      void'(uvm_config_db#(int)::get(null, "", "rst_delay", rst_delay));
     end
     initial #(rst_delay) rst_n = 1'b1;
 
     initial begin
+        uvm_config_db# (vif)::set(null,"*","if",mst_if);
         run_test();
     end
 

diff --git a/test/json/tb.json b/test/json/tb.json
@@ -5,7 +5,9 @@
         "vars": {
             "pkg_name": "spi_tb_lib",
             "import_pkgs":["spi_test_pkg"],
-            "test_pkg_name": "spi"
+            "if_name": "spi_if",
+            "filelist_pkgs":["spi_agt_pkg", "spi_env_pkg", "spi_seq_lib_pkg", "spi_test_pkg", "spi_tb_lib"]
+
         }
     }
 }