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Merge pull request #4 from GalaxyShad/decompiler-and-os-research
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@GalaxyShad
GalaxyShad authored Mar 25, 2024
2 parents 0832547 + f4493c8 commit 28aa42b
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8 changes: 8 additions & 0 deletions .clang-format
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TabWidth: 4
IndentWidth: 4

Language: Cpp

Standard: Cpp11

AccessModifierOffset: -4
4 changes: 3 additions & 1 deletion .gitignore
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Expand Up @@ -2,4 +2,6 @@
build/
lib/
docs/
CMakeCache.txt
CMakeCache.txt
.clangd
.cache/
11 changes: 10 additions & 1 deletion CMakeLists.txt
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cmake_minimum_required(VERSION 3.16)
project(umpk-80-emu-ui LANGUAGES CXX)


set(CMAKE_EXPORT_COMPILE_COMMANDS ON)

set(CMAKE_CXX_STANDARD 11)
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin)
option(BUILD_SHARED_LIBS "Build shared libraries" OFF)
Expand All @@ -14,7 +17,7 @@ FetchContent_MakeAvailable(SFML)

FetchContent_Declare(ImGui
GIT_REPOSITORY https://github.com/ocornut/imgui
GIT_TAG v1.89.9)
GIT_TAG v1.90.4-docking)
FetchContent_MakeAvailable(ImGui)
FetchContent_GetProperties(ImGui SOURCE_DIR IMGUI_DIR)

Expand All @@ -30,6 +33,12 @@ add_executable(umpk-80-emu-ui ${SOURCES})
target_link_libraries(umpk-80-emu-ui PRIVATE sfml-audio sfml-graphics ImGui-SFML::ImGui-SFML)
target_compile_features(umpk-80-emu-ui PRIVATE cxx_std_11)

target_compile_definitions(umpk-80-emu-ui
PRIVATE
# If the debug configuration pass the DEBUG define to the compiler
$<$<CONFIG:Debug>:DEBUG>
)

if(WIN32)
add_custom_command(
TARGET umpk-80-emu-ui
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197 changes: 0 additions & 197 deletions src/controller.hpp
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30 changes: 30 additions & 0 deletions src/core/_unused_time_period_table.hpp
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#include <stdint.h>

struct CpuTimePeriod {
char str[20];
uint8_t main;
uint8_t ifcond = 0;
};


const CpuTimePeriod _numbersOfTimePeriods[256] = {
// 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F //
/* 0x00 */ {"nop", 4}, {"lxi B,D16", 10}, {"stax B", 7}, {"inx B", 5}, {"inr B", 5}, {"dcr B", 5}, {"mvi B", 7}, {"rlc", 4}, {"UNKI", 1}, {"dad B", 10}, {"ldax B", 7}, {"dcx B", 5}, {"inr C", 5}, {"dcr C", 5}, {"mvi C", 7}, {"rrc", 4}, // 0x00
/* 0x01 */ {"UNKI", 4}, {"lxi D,D16", 10}, {"stax D", 7}, {"inx D", 5}, {"inr D", 5}, {"dcr D", 5}, {"mvi D", 7}, {"ral", 4}, {"UNKI", 1}, {"dad D", 10}, {"ldax D", 7}, {"dcx D", 5}, {"inr E", 5}, {"dcr E", 5}, {"mvi E", 7}, {"rar", 4}, // 0x10
/* 0x02 */ {"UNKI", 4}, {"lxi H,D16", 10}, {"shld ADR", 16}, {"inx H", 5}, {"inr H", 5}, {"dcr H", 5}, {"mvi H", 7}, {"daa", 4}, {"UNKI", 1}, {"dad H", 10}, {"lhld ADR", 16}, {"dcx H", 5}, {"inr L", 5}, {"dcr L", 5}, {"mvi L", 7}, {"cma", 4}, // 0x20
/* 0x03 */ {"UNKI", 4}, {"lxi SP,D16", 10}, {"sta ADR", 13}, {"inx SP", 5}, {"inr M", 10}, {"dcr M", 10}, {"mvi M", 10}, {"stc", 4}, {"UNKI", 1}, {"dad SP", 10}, {"lda ADR", 13}, {"dcx SP", 5}, {"inr A", 5}, {"dcr A", 5}, {"mvi A", 7}, {"cmc", 4}, // 0x30
/* 0x04 */ {"mov B,B", 5}, {"mov B,C", 5}, {"mov B,D", 5}, {"mov B,E", 5}, {"mov B,H", 5}, {"mov B,L", 5}, {"mov B,M", 7}, {"mov B,A", 5}, {"mov C,B", 5}, {"mov C,C", 5}, {"mov C,D", 5}, {"mov C,E", 5}, {"mov C,H", 5}, {"mov C,L", 5}, {"mov C,M", 7}, {"mov C,A", 5}, // 0x40
/* 0x05 */ {"mov D,B", 5}, {"mov D,C", 5}, {"mov D,D", 5}, {"mov D,E", 5}, {"mov D,H", 5}, {"mov D,L", 5}, {"mov D,M", 7}, {"mov D,A", 5}, {"mov E,B", 5}, {"mov E,C", 5}, {"mov E,D", 5}, {"mov E,E", 5}, {"mov E,H", 5}, {"mov E,L", 5}, {"mov E,M", 7}, {"mov E,A", 5}, // 0x50
/* 0x06 */ {"mov H,B", 5}, {"mov H,C", 5}, {"mov H,D", 5}, {"mov H,E", 5}, {"mov H,H", 5}, {"mov H,L", 5}, {"mov H,M", 7}, {"mov H,A", 5}, {"mov L,B", 5}, {"mov L,C", 5}, {"mov L,D", 5}, {"mov L,E", 5}, {"mov L,H", 5}, {"mov L,L", 5}, {"mov L,M", 7}, {"mov L,A", 5}, // 0x60
/* 0x07 */ {"mov M,B", 7}, {"mov M,C", 7}, {"mov M,D", 7}, {"mov M,E", 7}, {"mov M,H", 7}, {"mov M,L", 7}, {"hlt", 7}, {"mov M,A", 7}, {"mov A,B", 5}, {"mov A,C", 5}, {"mov A,D", 5}, {"mov A,E", 5}, {"mov A,H", 5}, {"mov A,L", 5}, {"mov A,M", 7}, {"mov A,A", 5}, // 0x70
/* 0x08 */ {"add B", 4}, {"add C", 4}, {"add D", 4}, {"add E", 4}, {"add H", 4}, {"add L", 4}, {"add M", 7}, {"add A", 4}, {"adc B", 4}, {"adc C", 4}, {"adc D", 4}, {"adc E", 4}, {"adc H", 4}, {"adc L", 4}, {"adc M", 7}, {"adc A", 4}, // 0x80
/* 0x09 */ {"sub B", 4}, {"sub C", 4}, {"sub D", 4}, {"sub E", 4}, {"sub H", 4}, {"sub L", 4}, {"sub M", 7}, {"sub A", 4}, {"sbb B", 4}, {"sbb C", 4}, {"sbb D", 4}, {"sbb E", 4}, {"sbb H", 4}, {"sbb L", 4}, {"sbb M", 7}, {"sbb A", 4}, // 0x90
/* 0x0A */ {"ana B", 4}, {"ana C", 4}, {"ana D", 4}, {"ana E", 4}, {"ana H", 4}, {"ana L", 4}, {"ana M", 7}, {"ana A", 4}, {"xra B", 4}, {"xra C", 4}, {"xra D", 4}, {"xra E", 4}, {"xra H", 4}, {"xra L", 4}, {"xra M", 7}, {"xra A", 4}, // 0xA0
/* 0x0B */ {"ora B", 4}, {"ora C", 4}, {"ora D", 4}, {"ora E", 4}, {"ora H", 4}, {"ora L", 4}, {"ora M", 7}, {"ora A", 4}, {"cmp B", 4}, {"cmp C", 4}, {"cmp D", 4}, {"cmp E", 4}, {"cmp H", 4}, {"cmp L", 4}, {"cmp M", 7}, {"cmp A", 4}, // 0xB0
/* 0x0C */ {"rnz", 5, 11}, {"pop B", 10}, {"jnz ADR", 10}, {"jmp ADR", 10}, {"cnz ADR", 11, 17}, {"push B", 11}, {"adi D8", 7}, {"rst 0", 11}, {"rz", 5, 11}, {"ret", 10}, {"jz ADR", 10}, {"UNKI", 1}, {"cz ADR", 11, 17}, {"call ADR", 17}, {"aci D8", 7}, {"rst 1", 11}, // 0xC0
/* 0x0D */ {"rnc", 5, 11}, {"pop D", 10}, {"jnc ADR", 10}, {"out PORT", 10}, {"cnc ADR", 11, 17}, {"push D", 11}, {"sui D8", 7}, {"rst 2", 11}, {"rc", 5, 11}, {"UNKI", 1}, {"jc ADR", 10}, {"in PORT", 10}, {"cc ADR", 11, 17}, {"UNKI", 1}, {"sbi D8", 7}, {"rst 3", 11}, // 0xD0
/* 0x0E */ {"rpo", 5, 11}, {"pop H", 10}, {"jpo ADR", 10}, {"xthl", 18}, {"cpo ADR", 11, 17}, {"push H", 11}, {"ani D8", 7}, {"rst 4", 11}, {"rpe", 5, 11}, {"pchl", 5}, {"jpe ADR", 10}, {"xchg", 4}, {"cpe ADR", 11, 17}, {"UNKI", 1}, {"xri D8", 7}, {"rst 5", 11}, // 0xE0
/* 0x0F */ {"rp", 5, 11}, {"pop PSW", 10}, {"jp ADR", 10}, {"di", 4}, {"cp ADR", 11, 17}, {"push PSW", 11}, {"ori D8", 7}, {"rst 6", 11}, {"rm", 5, 11}, {"sphl", 5}, {"jm ADR", 10}, {"ei", 4}, {"cm ADR", 11, 17}, {"UNKI", 1}, {"cpi D8", 7}, {"rst 7", 11}, // 0xF0
// 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F //
};
4 changes: 3 additions & 1 deletion src/bus.hpp → src/core/bus.hpp
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Expand Up @@ -35,6 +35,9 @@ class Bus {
return _memory[adr & 0x0FFF];
}

const uint8_t& romFirst() { return _memory[0]; }
const uint8_t& ramFirst() { return _memory[0x0800]; }

void loadRom(const uint8_t* buff, size_t size) {
memcpy(_memory, buff, size);
}
Expand All @@ -58,7 +61,6 @@ class Bus {
}

uint8_t portIn(uint8_t port) {
// return 0x00;
return (_inDevices[port] != nullptr) ? _inDevices[port]->busPortRead() : 0x00;
}

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