GitHub - Hetsoni2002/MIPS_single_cycle_design_verilog: A mips processor design is aheived using design in verilog.

Hetsoni2002 / MIPS_single_cycle_design_verilog Public

A mips processor design is aheived using design in verilog.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALUControl.v		ALUControl.v
D_FF.v		D_FF.v
adder.v		adder.v
alu.v		alu.v
control.v		control.v
counter.v		counter.v
data_memory.v		data_memory.v
decoder.v		decoder.v
instr_mem.v		instr_mem.v
interna_xor_5bitlfsr.v		interna_xor_5bitlfsr.v
mips_16.v		mips_16.v
mux2x5to5.v		mux2x5to5.v
pc_reg.v		pc_reg.v
register_file.v		register_file.v
tb.v		tb.v