Update hillside52_right.overlay

config/boards/shields/hillside52/hillside52_right.overlay

@@ -33,3 +33,262 @@
 &right_encoder {
     status = "okay";
 };
+
+/*
+ * PS/2 Mouse / Trackpoint
+ */
+
+// Enable PS/2 drivers on this side of the keyboard.
+// MUST be the central.
+//
+// Comment out the following define to use the GPIO driver instead of UART
+// (this is not recommended unless you can't use the UART driver for whatever
+// reason)
+#define MOUSE_PS2_DRIVER_UART
+
+#ifdef MOUSE_PS2_DRIVER_UART
+    &uart0 {
+        status = "okay";
+    };
+    &uart_ps2 {
+        status = "okay";
+    };
+#else
+    &gpio_ps2 {
+        status = "okay";
+    };
+#endif
+
+&mouse_ps2 {
+	status = "okay";
+
+#ifdef MOUSE_PS2_DRIVER_UART
+	ps2-device = <&uart_ps2>;
+#else
+	ps2-device = <&gpio_ps2>;
+#endif
+};
+
+&mouse_ps2_input_listener {
+    status = "okay";
+
+    // Some of the available settings depend on the keymap. So they
+    // are adjusted in...
+    // ../../../includes/trackpoint.dtsi
+};
+
+// Adjust GPIO interrupt priority to the highest level.
+//
+// PS/2 events must be processed within 30-50us, but frequently bluetooth and
+// other interrupts take longer to finish.
+//
+// Therefore we change the default GPIO priority to the highest level (0) and
+// demote all BT interrupt priorities by one level using the kconfig settings:
+// - CONFIG_BT_CTLR_LLL_PRIO 1
+// - CONFIG_BT_CTLR_ULL_HIGH_PRIO 2
+// - CONFIG_BT_CTLR_ULL_LOW_PRIOCONFIG 2
+//
+// These config options are enabled automatically by the PS2 UART and GPIO
+// drivers... so you don't have to enable them manually.
+//
+// Then we lower the interrupt priority of all other devices by 2 levels using
+// the devicetree config below.
+//
+// This allows the PS/2 interrupts to be triggered faster and reduces
+// transmission errors.
+//
+// If you are using the nice_nano_v2 board, you can reuse my config below.
+//
+// Otherwise, you can generate the interrupt overrides using the following
+// script in my zmk fork with the PS/2 mouse driver:
+// app/scripts/gen_interrupt_priority_overrides.py
+//
+// Make sure to do it on a zephyr.dts where the interrupts have not been
+// adjusted yet (i.e. a config that doesn't have the the following options
+// enabled).
+//
+// If you are building using a toolchain you can find the zephyr.dts in the
+// build directory, which by default is: `app/build/zephyr/zephyr.dts`
+//
+// If you are building using the github actions, copy the output of the build
+// step `xxxx_right - nice_nano_v2 Devicetree file` into a file and run the
+// script on it.
+
+// gpiote should have the highest interrupt priority (0)
+&gpiote {
+    interrupts = < 6 0 >;
+};
+
+// All other priorities should be two levels lower than their defaults
+// (which is usually 1 and should be demoted to 3)
+&clock {
+    interrupts = < 0 3 >;
+};
+
+&power {
+    interrupts = < 0 3 >;
+};
+
+&radio {
+    interrupts = < 1 3 >;
+};
+
+&uart0 {
+    interrupts = < 2 3 >;
+};
+
+&i2c0 {
+    interrupts = < 3 3 >;
+};
+
+&spi0 {
+    interrupts = < 3 3 >;
+};
+
+&i2c1 {
+    interrupts = < 4 3 >;
+};
+
+&spi1 {
+    interrupts = < 4 3 >;
+};
+
+&nfct {
+    interrupts = < 5 3 >;
+};
+
+&adc {
+    interrupts = < 7 3 >;
+};
+
+&timer0 {
+    interrupts = < 8 3 >;
+};
+
+&timer1 {
+    interrupts = < 9 3 >;
+};
+
+&timer2 {
+    interrupts = < 10 3 >;
+};
+
+&rtc0 {
+    interrupts = < 11 3 >;
+};
+
+&temp {
+    interrupts = < 12 3 >;
+};
+
+&rng {
+    interrupts = < 13 3 >;
+};
+
+&ecb {
+    interrupts = < 14 3 >;
+};
+
+&ccm {
+    interrupts = < 15 3 >;
+};
+
+&wdt {
+    interrupts = < 16 3 >;
+};
+
+&rtc1 {
+    interrupts = < 17 3 >;
+};
+
+&qdec {
+    interrupts = < 18 3 >;
+};
+
+&comp {
+    interrupts = < 19 3 >;
+};
+
+&egu0 {
+    interrupts = < 20 3 >;
+};
+
+&egu1 {
+    interrupts = < 21 3 >;
+};
+
+&egu2 {
+    interrupts = < 22 3 >;
+};
+
+&egu3 {
+    interrupts = < 23 3 >;
+};
+
+&egu4 {
+    interrupts = < 24 3 >;
+};
+
+&egu5 {
+    interrupts = < 25 3 >;
+};
+
+&timer3 {
+    interrupts = < 26 3 >;
+};
+
+&timer4 {
+    interrupts = < 27 3 >;
+};
+
+&pwm0 {
+    interrupts = < 28 3 >;
+};
+
+&pdm0 {
+    interrupts = < 29 3 >;
+};
+
+&pwm1 {
+    interrupts = < 33 3 >;
+};
+
+&pwm2 {
+    interrupts = < 34 3 >;
+};
+
+&spi2 {
+    interrupts = < 35 3 >;
+};
+
+&rtc2 {
+    interrupts = < 36 3 >;
+};
+
+&i2s0 {
+    interrupts = < 37 3 >;
+};
+
+&usbd {
+    interrupts = < 39 3 >;
+};
+
+&uart1 {
+    interrupts = < 40 3 >;
+};
+
+&qspi {
+    interrupts = < 41 3 >;
+};
+
+&pwm3 {
+    interrupts = < 45 3 >;
+};
+
+&spi3 {
+    interrupts = < 47 3 >;
+};
+
+&cryptocell {
+    interrupts = < 42 3 >;
+};