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make BRAM debugging testbenches
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SinaKarvandi committed May 1, 2024
1 parent e46e9c1 commit 090b2b0
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1 change: 1 addition & 0 deletions sim/hwdbg/DebuggerModuleTestingBRAM/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerMain.sv
VERILOG_SOURCES += $(shell pwd)/../../../generated/SendReceiveSynchronizer.sv
VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketReceiver.sv
VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketSender.sv
VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketInterpreter.sv
TOPLEVEL = DebuggerModuleTestingBRAM
MODULE = test_DebuggerModuleTestingBRAM

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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,78 @@
from cocotb.triggers import RisingEdge
from cocotb.types import LogicArray

'''
input clock,
reset,
io_en,
io_inputPin_0,
io_inputPin_1,
io_inputPin_2,
io_inputPin_3,
io_inputPin_4,
io_inputPin_5,
io_inputPin_6,
io_inputPin_7,
io_inputPin_8,
io_inputPin_9,
io_inputPin_10,
io_inputPin_11,
io_inputPin_12,
io_inputPin_13,
io_inputPin_14,
io_inputPin_15,
io_inputPin_16,
io_inputPin_17,
io_inputPin_18,
io_inputPin_19,
io_inputPin_20,
io_inputPin_21,
io_inputPin_22,
io_inputPin_23,
io_inputPin_24,
io_inputPin_25,
io_inputPin_26,
io_inputPin_27,
io_inputPin_28,
io_inputPin_29,
io_inputPin_30,
io_inputPin_31,
output io_outputPin_0,
io_outputPin_1,
io_outputPin_2,
io_outputPin_3,
io_outputPin_4,
io_outputPin_5,
io_outputPin_6,
io_outputPin_7,
io_outputPin_8,
io_outputPin_9,
io_outputPin_10,
io_outputPin_11,
io_outputPin_12,
io_outputPin_13,
io_outputPin_14,
io_outputPin_15,
io_outputPin_16,
io_outputPin_17,
io_outputPin_18,
io_outputPin_19,
io_outputPin_20,
io_outputPin_21,
io_outputPin_22,
io_outputPin_23,
io_outputPin_24,
io_outputPin_25,
io_outputPin_26,
io_outputPin_27,
io_outputPin_28,
io_outputPin_29,
io_outputPin_30,
io_outputPin_31,
input io_plInSignal,
output io_psOutInterrupt
'''

@cocotb.test()
async def DebuggerModuleTestingBRAM_test(dut):
"""Test hwdbg module (with pre-defined BRAM)"""
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15 changes: 11 additions & 4 deletions src/main/scala/hwdbg/communication/interpreter/interpreter.scala
Original file line number Diff line number Diff line change
Expand Up @@ -111,13 +111,20 @@ class DebuggerPacketInterpreter(
// Check if the debugger need a new action (a new command is received)
//
when(io.requestedActionOfThePacketInputValid) {

//
// An action is received
//
state := sNewActionReceived

}.otherwise {

//
// Remain at the same state (no action)
//
state := sDone
}

//
// Remain at the same state
//
state := sDone
}
is(sNewActionReceived) {

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2 changes: 1 addition & 1 deletion src/main/scala/top.scala
Original file line number Diff line number Diff line change
Expand Up @@ -104,7 +104,7 @@ object Main extends App {
),
firtoolOpts = Array(
"-disable-all-randomization",
"-strip-debug-info",
// "-strip-debug-info",
"--split-verilog", // The intention for this argument (and next argument) is to separate generated files.
"-o",
"generated/"
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1 change: 1 addition & 0 deletions src/main/scala/top_test.scala
Original file line number Diff line number Diff line change
Expand Up @@ -135,6 +135,7 @@ object MainWithInitializedBRAM extends App {
),
firtoolOpts = Array(
"-disable-all-randomization",
"-strip-debug-info",
"--lowering-options=disallowLocalVariables", // because icarus doesn't support 'automatic logic', this option prevents such logics
"--split-verilog", // The intention for this argument (and next argument) is to separate generated files.
"-o",
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