change the testbench of the receiver to apply valid indicator

HyperDbg · Apr 22, 2024 · 729c1e2 · 729c1e2
1 parent 7b1fbef
commit 729c1e2
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/sim/hwdbg/communication/DebuggerPacketReceiver/test_DebuggerPacketReceiver.py b/sim/hwdbg/communication/DebuggerPacketReceiver/test_DebuggerPacketReceiver.py
@@ -45,10 +45,10 @@ async def DebuggerPacketReceiver_test(dut):
     # Assert initial output is unknown
     #
     assert LogicArray(dut.io_rdWrAddr.value) == LogicArray("XXXXXXXXXXXXX")
-    assert LogicArray(dut.io_requestedActionOfThePacketOutput.value) == LogicArray("XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX")
+    assert LogicArray(dut.io_requestedActionOfThePacketOutput.value) == LogicArray("ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ")
     assert LogicArray(dut.io_requestedActionOfThePacketOutputValid.value) == LogicArray("X")
     assert LogicArray(dut.io_dataValidOutput.value) == LogicArray("X")
-    assert LogicArray(dut.io_receivingData.value) == LogicArray("XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX")
+    assert LogicArray(dut.io_receivingData.value) == LogicArray("ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ")
     assert LogicArray(dut.io_finishedReceivingBuffer.value) == LogicArray("X")
 
     clock = Clock(dut.clock, 10, units="ns")  # Create a 10ns period clock on port clock
@@ -104,7 +104,7 @@ async def DebuggerPacketReceiver_test(dut):
                     case 0x0: # checksum
                         dut.io_rdData.value = 0x00001234
                     case 0x8: # indicator
-                        dut.io_rdData.value = 0x88888888
+                        dut.io_rdData.value = 0x48595045 # first 32 bits of the indicator
                     case 0x10: # type
                         dut.io_rdData.value = 0x10101010
                     case 0x14: # requested action

diff --git a/src/main/scala/hwdbg/communication/receiver.scala b/src/main/scala/hwdbg/communication/receiver.scala
@@ -181,7 +181,7 @@ class DebuggerPacketReceiver(
         // Check whether the indicator is valid or not
         //
         LogInfo(debug)(
-          f"Comparing first 0x${BitwiseFunction.printFirstNBits(HyperDbgSharedConstants.INDICATOR_OF_HYPERDBG_PACKET, bramDataWidth)}%x bits of the indicator"
+          f"Comparing first 0x${BitwiseFunction.printFirstNBits(HyperDbgSharedConstants.INDICATOR_OF_HYPERDBG_PACKET, bramDataWidth)}%x number of the indicator"
         )
         when(io.rdData === BitwiseFunction.printFirstNBits(HyperDbgSharedConstants.INDICATOR_OF_HYPERDBG_PACKET, bramDataWidth).U) {