connect BRAM data to external IO output

HyperDbg · Apr 14, 2024 · da30765 · da30765
1 parent 7543aa9
commit da30765
Show file tree

Hide file tree

Showing 3 changed files with 3 additions and 61 deletions.
diff --git a/src/main/scala/hwdbg/configs/configs.scala b/src/main/scala/hwdbg/configs/configs.scala
@@ -30,12 +30,12 @@ object DebuggerConfigurations {
   //
   // Number of input pins
   //
-  val NUMBER_OF_INPUT_PINS: Int = 16
+  val NUMBER_OF_INPUT_PINS: Int = 32
 
   //
   // Number of output pins
   //
-  val NUMBER_OF_OUTPUT_PINS: Int = 16
+  val NUMBER_OF_OUTPUT_PINS: Int = 32
 
   //
   // Address width of the Block RAM (BRAM)

diff --git a/src/main/scala/hwdbg/main.scala b/src/main/scala/hwdbg/main.scala
@@ -79,7 +79,7 @@ class DebuggerMain(
   // Configure the output signals
   //
   for (i <- 0 until numberOfOutputPins) {
-    io.outputPin(i) := 0.U
+    io.outputPin(i) := requestedActionOfThePacket(i)
   }
 
   io.rdWrAddr := rdWrAddr

diff --git a/src/test/scala/hwdbg/tb_top_test.scala b/src/test/scala/hwdbg/tb_top_test.scala