reconfigure testbench for main with BRAM

HyperDbg · Apr 23, 2024 · f22f6fe · f22f6fe
1 parent 0c4edb6
commit f22f6fe
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Showing 3 changed files with 9 additions and 26 deletions.
diff --git a/sim/hwdbg/DebuggerModuleTestingBRAM/Makefile b/sim/hwdbg/DebuggerModuleTestingBRAM/Makefile
@@ -1,7 +1,12 @@
 # Makefile
 
 TOPLEVEL_LANG = verilog
-VERILOG_SOURCES = $(shell pwd)/../../../generated/DebuggerModuleTestingBRAM.sv
+VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerModuleTestingBRAM.sv
+VERILOG_SOURCES += $(shell pwd)/../../../generated/InitRegMemFromFile.sv
+VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerMain.sv
+VERILOG_SOURCES += $(shell pwd)/../../../generated/SendReceiveSynchronizer.sv
+VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketReceiver.sv
+VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketSender.sv
 TOPLEVEL = DebuggerModuleTestingBRAM
 MODULE = test_DebuggerModuleTestingBRAM
 

diff --git a/src/main/scala/hwdbg/communication/send_receive_synchronizer.scala b/src/main/scala/hwdbg/communication/send_receive_synchronizer.scala
@@ -386,27 +386,3 @@ object SendReceiveSynchronizer {
     )
   }
 }
-
-object SendReceiveSynchronizerModule extends App {
-
-  //
-  // Generate hwdbg verilog files
-  //
-  println(
-    ChiselStage.emitSystemVerilog(
-      new SendReceiveSynchronizer(
-        DebuggerConfigurations.ENABLE_DEBUG,
-        DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
-        DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
-      ),
-      firtoolOpts = Array(
-        "-disable-all-randomization",
-        "--lowering-options=disallowLocalVariables", // because icarus doesn't support 'automatic logic', this option prevents such logics
-        "-strip-debug-info",
-        "--split-verilog", // The intention for this argument (and next argument) is to separate generated files.
-        "-o",
-        "generated/"
-      )
-    )
-  )
-}
diff --git a/src/main/scala/hwdbg/libs/mem/init_reg_mem_from_file.scala b/src/main/scala/hwdbg/libs/mem/init_reg_mem_from_file.scala
@@ -30,6 +30,7 @@ object InitRegMemFromFileTools {
       width: Int
   ): Seq[UInt] = {
 
+    var counter: Int = 0
     val buffer = new ArrayBuffer[UInt]
     for (line <- Source.fromFile(path).getLines()) {
       val tokens: Array[String] = line.split("(//)").map(_.trim)
@@ -38,9 +39,10 @@ object InitRegMemFromFileTools {
         val i = Integer.parseInt(tokens.head, 16)
 
         LogInfo(debug)(
-          f"Initialize memory with 0x${i}%x"
+          f"Initialize memory [${counter}%x]: 0x${i}%x"
         )
 
+        counter = counter + 4
         buffer.append(i.U(width.W))
       }
     }