fix configuration bit problem after FPGA-Research-Manchester#242

FABulous/fabric_generator/fabric_gen.py

@@ -704,7 +704,7 @@ def genTileSwitchMatrix(self, tile: Tile) -> None:
                     )
 
                 # update the configuration bitstream position
-                configBitstreamPosition += len(connections[portName]).bit_length() - 1
+                configBitstreamPosition += paddedMuxSize.bit_length() - 1
 
         ### SwitchMatrixDebugSignals ### SwitchMatrixDebugSignals ###
         ### SwitchMatrixDebugSignals ### SwitchMatrixDebugSignals ###