gen tile

FABulous/fabric_cad/chip.py

@@ -248,6 +248,8 @@ def create_bel(self, name: str, type: str, z: int):
     def add_bel_pin(self, bel: BelData, pin: str, wire: str, dir: PinType):
         # Add a pin with associated wire to a bel. The wire should exist already.
         pin_id = self.strs.id(pin)
+        if self.strs.id(wire) not in self._wire2idx:
+            raise ValueError(f"Wire {wire} not found")
         wire_idx = self._wire2idx[self.strs.id(wire)]
         bel.pins.append(BelPin(pin_id, wire_idx, dir))
         self.wires[wire_idx].bel_pins.append(BelPinRef(bel.index, pin_id))

FABulous/fabric_cad/chip_database_generation.py

@@ -0,0 +1,90 @@
+import os
+from pathlib import Path
+
+from loguru import logger
+
+from FABulous.fabric_cad.chip import Chip, PinType, TileType
+from FABulous.fabric_definition.Bel import Bel
+from FABulous.fabric_definition.Fabric import Fabric
+from FABulous.fabric_definition.Tile import Tile
+from FABulous.fabric_generator.code_generation_Verilog import VerilogWriter
+from FABulous.fabric_generator.file_parser import parseMatrixAsMux
+from FABulous.FABulous_API import FABulous
+
+
+def genSwitchMatrix(tile: Tile, tileType: TileType):
+    muxDict = parseMatrixAsMux(
+        Path("/home/kelvin/FABulous_fork/demo/Tile/LUT4AB/LUT4AB_switch_matrix.csv"),
+        tile.name,
+    )
+
+    for mux in muxDict.values():
+        for i in mux.inputs:
+            tileType.create_wire(i, f"SWITCH_{tile.name}")
+        tileType.create_wire(mux.output, f"SWITCH_{tile.name}")
+
+    for mux in muxDict.values():
+        for s in mux.inputs:
+            tileType.create_pip(s, mux.output, timing_class="SWINPUT")
+
+
+def genBel(bels: list[Bel], tile: TileType):
+    for z, bel in enumerate(bels):
+        if bel.withUserCLK:
+            tile.create_wire("UserCLK", f"{bel.name}_UserCLK")
+
+        # create the bel itself
+        belData = tile.create_bel(f"{bel.prefix}{bel.name}", bel.name, z)
+
+        for i in bel.inputs + bel.externalInput:
+            tile.add_bel_pin(
+                belData,
+                f"{i.removeprefix(bel.prefix)}",
+                i,
+                PinType.INPUT,
+            )
+        for i in bel.outputs + bel.externalOutput:
+            tile.add_bel_pin(
+                belData,
+                f"{i.removeprefix(bel.prefix)}",
+                i,
+                PinType.OUTPUT,
+            )
+
+        # if bel.withUserCLK:
+        #     tile.add_bel_pin(
+        #         belData,
+        #         "UserCLK",
+        #         f"{bel.name}_UserCLK",
+        #         PinType.INPUT,
+        #     )
+
+
+def genTile(tile: Tile, chip: Chip) -> TileType:
+    tt = chip.create_tile_type(tile.name)
+    genSwitchMatrix(tile, tt)
+    genBel(tile.bels, tt)
+    return tt
+
+
+def genChipDatabase(fabric: Fabric):
+    ch = Chip("FABulous", fabric.name, fabric.numberOfRows, fabric.numberOfColumns)
+
+
+    if p := os.getenv("FAB_PROJ_DIR"):
+        ch.write_bba(str(Path(p) / f"{fabric.name}.bba"))
+    else:
+        logger.error("FAB_PROJ_DIR not set, cannot write bba file")
+        return
+
+
+if __name__ == "__main__":
+    f = FABulous(VerilogWriter(), "/home/kelvin/FABulous_fork/demo/fabric.csv")
+    f.setWriterOutputFile("/home/kelvin/FABulous_fork/test.v")
+    f.bootstrapSwitchMatrix("LUT4AB", "/home/kelvin/FABulous_fork/tmp.csv")
+    f.loadFabric("/home/kelvin/FABulous_fork/demo/fabric.csv")
+    f.genFabric()
+    ch = Chip(
+        "FABulous", f.fabric.name, f.fabric.numberOfRows, f.fabric.numberOfColumns
+    )
+    genTile(f.fabric.tileDic["LUT4AB"], ch)

FABulous/fabric_definition/Mux.py

@@ -0,0 +1,8 @@
+from dataclasses import dataclass
+
+@dataclass
+class Mux:
+    name: str
+    inputs: list[str]
+    output: str
+    width: int

FABulous/fabric_definition/SwitchMatrix.py

@@ -0,0 +1,10 @@
+from dataclasses import dataclass, field
+from FABulous.fabric_definition.Mux import Mux
+
+@dataclass
+class SwitchMatrix:
+    muxes: list[Mux] = field(default_factory=list)
+    wires: list[str] = field(default_factory=list)
+
+
+

FABulous/fabric_generator/file_parser.py

@@ -14,6 +14,7 @@
 from FABulous.fabric_definition.SuperTile import SuperTile
 from FABulous.fabric_definition.Fabric import Fabric
 from FABulous.fabric_definition.ConfigMem import ConfigMem
+from FABulous.fabric_definition.Mux import Mux
 from FABulous.fabric_definition.define import (
     IO,
     Direction,
@@ -281,6 +282,31 @@ def parseMatrix(fileName: Path, tileName: str) -> dict[str, list[str]]:
     return connectionsDic
 
 
+def parseMatrixAsMux(fileName: Path, tileName: str) -> dict[str, Mux]:
+    connectionsDic = {}
+    with open(fileName, "r") as f:
+        file = f.read()
+        file = re.sub(r"#.*", "", file)
+        file = file.split("\n")
+
+    if file[0].split(",")[0] != tileName:
+        logger.error(f"{fileName} {file[0].split(',')} {tileName}")
+        logger.error(
+            "Tile name (top left element) in csv file does not match tile name in tile object"
+        )
+        raise ValueError
+    destList = file[0].split(",")[1:]
+
+    for i in file[1:]:
+        i = i.split(",")
+        portName, connections = i[0], i[1:]
+        if portName == "":
+            continue
+        indices = [k for k, v in enumerate(connections) if v == "1"]
+        connectionsDic[portName] = Mux(f"{tileName}_{portName}", [destList[j] for j in indices], portName, 1)
+    return connectionsDic
+
+
 @overload
 def parseList(
     filePath: Path, collect: Literal["pair"] = "pair", prefix: str = ""