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!src | ||
/* | ||
!src/ | ||
!build.sbt | ||
!.gitignore |
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// build.sbt | ||
scalaVersion := "2.13.8" | ||
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.0" cross CrossVersion.full) | ||
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.5.0" | ||
// We also recommend using chiseltest for writing unit tests | ||
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.0" % "test" |
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import pipeline._ | ||
import chisel3._ | ||
import chisel3.stage._ | ||
import funcunit._ | ||
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object Build extends App { | ||
// println(getVerilogString(new InstFetch)) | ||
println("Generating Verilog Code") | ||
(new ChiselStage).emitVerilog(new Alu) | ||
println("Done") | ||
} |
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import chisel3._ | ||
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object FIR extends App { | ||
// println("[{(Generating Verilog file)}]") | ||
// (new ChiselStage).emitVerilog(new FIR(0, 0, 0, 0)) | ||
} | ||
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class FIR(b0: Int, b1: Int, b2: Int, b3: Int) extends Module { | ||
val io = IO(new Bundle() { | ||
val in = Input(UInt(8.W)) | ||
val out = Output(UInt(8.W)) | ||
}) | ||
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val shift_0 = RegNext(io.in, 0.U) | ||
val shift_1 = RegNext(shift_0, 0.U) | ||
val shift_2 = RegNext(shift_1, 0.U) | ||
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io.out := io.in * b0.U(8.W) + | ||
shift_0 * b1.U(8.W) + | ||
shift_1 * b2.U(8.W) + | ||
shift_2 * b3.U(8.W) | ||
} |
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import chisel3._ | ||
import chisel3.stage._ | ||
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object HelloWorld extends App { | ||
println("[{(Generating Verilog file)}]") | ||
(new ChiselStage).emitVerilog(new Alu) | ||
// println(getVerilogString(new Alu)) | ||
} | ||
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class Alu extends Module { | ||
val io = IO(new Bundle{ | ||
val src_a = Input(UInt(32.W)) | ||
val src_b = Input(UInt(32.W)) | ||
val op_code = Input(UInt(12.W)) | ||
val res = Output(UInt(32.W)) | ||
}) | ||
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when(io.op_code(0)) { | ||
io.res := io.src_a + io.src_b | ||
}.otherwise { | ||
io.res := io.src_a - io.src_b | ||
} | ||
} |
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import pipeline._ | ||
import chisel3._ | ||
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class Top extends Module { | ||
val sram_req = IO(new SramReq) | ||
val sram_res = IO(new SramRes) | ||
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val pfs = Module(new PreInstFetch) | ||
val fs = Module(new InstFetch) | ||
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pfs.sram_req <> sram_req | ||
pfs.pfs2fs_bus <> fs.pfs2fs_bus | ||
fs.sram_res <> sram_res | ||
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fs.fs2ds_bus.ds_allowin := true.B | ||
} |
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package funcunit | ||
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import chisel3._ | ||
import chisel3.util._ | ||
import pipeline._ | ||
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class Alu extends Module { | ||
val io = IO(Flipped(new DsToAluBus)) | ||
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val res = Wire(Vec(12, UInt(32.W))) | ||
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res(0) := io.src1 + io.src2 | ||
res(1) := io.src1 - io.src2 | ||
res(2) := io.src1 & io.src2 | ||
res(3) := io.src1 | io.src2 | ||
res(4) := io.src1 ^ io.src2 | ||
res(5) := ~(io.src1 | io.src2) | ||
res(6) := io.src1 + io.src2 | ||
res(7) := io.src1 + io.src2 | ||
res(8) := io.src1 + io.src2 | ||
res(9) := io.src1 + io.src2 | ||
res(10) := io.src1 + io.src2 | ||
res(11) := io.src1 + io.src2 | ||
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io.res := Mux1H(io.aluop, res) | ||
} |
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package funcunit | ||
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import chisel3._ | ||
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class RegFile(NRReg: Int, XLen: Int) extends Module { | ||
def log2(x: Double): Int = (Math.log(x) / Math.log(2)).toInt | ||
val addr_len = log2(NRReg) | ||
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val io = IO(new Bundle() { | ||
val raddr = Input(Vec(2, UInt(addr_len.W))) | ||
val rdata = Output(Vec(2, UInt(XLen.W))) | ||
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val wen = Input(Bool()) | ||
val waddr = Input(UInt(addr_len.W)) | ||
val wdata = Input(UInt(XLen.W)) | ||
}) | ||
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val regs = Mem(NRReg, UInt(XLen.W)) | ||
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when (io.wen) { | ||
regs(io.waddr) := io.wdata | ||
} | ||
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for (i <- 0 to 1) { | ||
when (io.raddr(i) === "h0".U(5.W)) { | ||
io.rdata(i) := "h0".U(32.W) | ||
} otherwise { | ||
io.rdata(i) := regs(io.raddr(i)) | ||
} | ||
} | ||
} |
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package pipeline | ||
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import chisel3._ | ||
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class Decode extends Module { | ||
// Interface | ||
val fs2ds_bus = IO(Flipped(new FsToDsBus)) | ||
val ds2es_bus = IO(new DsToEsBus) | ||
val ds2alu_bus = IO(new DsToAluBus) | ||
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// Stage Control | ||
val valid = RegInit(false.B) | ||
val ds_ready_go = Wire(Bool()) | ||
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// Stage Register | ||
val data = Reg(new FsToDsData) | ||
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// Functional Part | ||
val inst_add_w = Wire(Bool()) | ||
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fs2ds_bus.ds_allowin := ~valid | ds_ready_go & ds2es_bus.es_allowin | ||
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ds2es_bus.ds_valid := valid & ds_ready_go | ||
ds2es_bus.data.pc := data.pc | ||
ds2es_bus.data.dest := "h0".U(5.W) | ||
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ds2alu_bus.src1 := "h0".U(32.W) | ||
ds2alu_bus.src2 := "h0".U(32.W) | ||
ds2alu_bus.aluop(0) := inst_add_w | ||
ds2alu_bus.aluop(1) := inst_add_w | ||
ds2alu_bus.aluop(2) := inst_add_w | ||
ds2alu_bus.aluop(3) := inst_add_w | ||
ds2alu_bus.aluop(4) := inst_add_w | ||
ds2alu_bus.aluop(5) := inst_add_w | ||
ds2alu_bus.aluop(6) := inst_add_w | ||
ds2alu_bus.aluop(7) := inst_add_w | ||
ds2alu_bus.aluop(8) := inst_add_w | ||
ds2alu_bus.aluop(9) := inst_add_w | ||
ds2alu_bus.aluop(10) := inst_add_w | ||
ds2alu_bus.aluop(11) := inst_add_w | ||
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ds_ready_go := true.B | ||
when (fs2ds_bus.ds_allowin) { | ||
valid := fs2ds_bus.fs_valid | ||
} | ||
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when (fs2ds_bus.fs_valid && fs2ds_bus.ds_allowin) { | ||
data := fs2ds_bus.data | ||
} | ||
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inst_add_w := fs2ds_bus.data.inst(1, 0) === 2.U | ||
} |
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package pipeline | ||
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import chisel3._ | ||
import chisel3.stage | ||
import chisel3.stage.ChiselStage | ||
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class InstFetch extends Module { | ||
// Interface | ||
val pfs2fs_bus = IO(Flipped(new PfsToFsBus)) | ||
val fs2ds_bus = IO(new FsToDsBus) | ||
val sram_res = IO(new SramRes) | ||
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// Stage Control | ||
val valid = RegInit(false.B) | ||
val fs_ready_go = Wire(Bool()) | ||
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// Stage Register | ||
val data = Reg(new PfsToFsData) | ||
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pfs2fs_bus.fs_allowin := ~valid | fs_ready_go & fs2ds_bus.ds_allowin | ||
fs2ds_bus.fs_valid := valid & fs_ready_go | ||
fs2ds_bus.data.inst := sram_res.rdata | ||
fs2ds_bus.data.pc := data.pc | ||
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fs_ready_go := true.B | ||
when (pfs2fs_bus.fs_allowin) { | ||
valid := pfs2fs_bus.pfs_valid | ||
} | ||
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when (pfs2fs_bus.pfs_valid && pfs2fs_bus.fs_allowin) { | ||
data := pfs2fs_bus.data | ||
} | ||
} |
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package pipeline | ||
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import chisel3._ | ||
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// sram insterface | ||
class SramReq extends Bundle { | ||
val en = Output(Bool()) | ||
val wen = Output(UInt(4.W)) | ||
val addr = Output(UInt(32.W)) | ||
val wdata = Output(UInt(32.W)) | ||
} | ||
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class SramRes extends Bundle { | ||
val rdata = Input(UInt(32.W)) | ||
} | ||
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// pre-inst-fetch and inst-fetch | ||
class PfsToFsData extends Bundle { | ||
val pc = Output(UInt(32.W)) | ||
} | ||
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class PfsToFsBus extends Bundle { | ||
val fs_allowin = Input(Bool()) | ||
val pfs_valid = Output(Bool()) | ||
val data = new PfsToFsData | ||
} | ||
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// inst-fetch and decode | ||
class FsToDsData extends Bundle { | ||
val pc = Output(UInt(32.W)) | ||
val inst = Output(UInt(32.W)) | ||
} | ||
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class FsToDsBus extends Bundle { | ||
val ds_allowin = Input(Bool()) | ||
val fs_valid = Output(Bool()) | ||
val data = new FsToDsData | ||
} | ||
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// decode and execute | ||
class DsToEsData extends Bundle { | ||
val pc = Output(UInt(32.W)) | ||
val dest = Output(UInt(5.W)) | ||
} | ||
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class DsToAluBus extends Bundle { | ||
val src1 = Output(UInt(32.W)) | ||
val src2 = Output(UInt(32.W)) | ||
// val aluop = Output(Vec(12, Bool())) | ||
val aluop = Output(UInt(12.W)) | ||
val res = Input(UInt(32.W)) | ||
} | ||
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class DsToEsBus extends Bundle { | ||
val es_allowin = Input(Bool()) | ||
val ds_valid = Output(Bool()) | ||
val data = new DsToEsData | ||
} |
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package pipeline | ||
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import chisel3._ |
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package pipeline | ||
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import chisel3._ | ||
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class PreInstFetch extends Module { | ||
// Interface | ||
val pfs2fs_bus = IO(new PfsToFsBus) | ||
val sram_req = IO(new SramReq) | ||
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// Stage Control | ||
val to_pfs_valid = Wire(Bool()) | ||
val pfs_allowin = Wire(Bool()) | ||
val valid = RegInit(false.B) | ||
val pfs_ready_go = Wire(Bool()) | ||
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// Stage Register | ||
val data = RegInit("h1bff_fffc".U(32.W)) | ||
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pfs2fs_bus.pfs_valid := valid & pfs_ready_go | ||
pfs2fs_bus.data.pc := data | ||
sram_req.en := to_pfs_valid & pfs_allowin | ||
sram_req.wen := "h0".U(4.W) | ||
sram_req.addr := data | ||
sram_req.wdata := "h0000_0000".U(32.W) | ||
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to_pfs_valid := true.B | ||
pfs_allowin := ~valid | pfs_ready_go & pfs2fs_bus.fs_allowin | ||
pfs_ready_go := true.B | ||
when (pfs_allowin) { | ||
valid := to_pfs_valid | ||
} | ||
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when (to_pfs_valid && pfs_allowin) { | ||
data := data + "h4".U(32.W) | ||
} | ||
} |
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import chisel3._ | ||
import chiseltest._ | ||
import org.scalatest.flatspec.AnyFlatSpec | ||
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class FIRtest extends AnyFlatSpec with ChiselScalatestTester { | ||
behavior of "FIR" | ||
// test class body here | ||
it should "test all zero" in { | ||
// test case body here | ||
test(new FIR(0, 0, 0, 0)) { c => | ||
c.io.in.poke(0.U) | ||
c.io.out.expect(0.U) | ||
c.clock.step(1) | ||
c.io.in.poke(4.U) | ||
c.io.out.expect(0.U) | ||
c.clock.step(1) | ||
c.io.in.poke(5.U) | ||
c.io.out.expect(0.U) | ||
c.clock.step(1) | ||
c.io.in.poke(2.U) | ||
c.io.out.expect(0.U) | ||
} | ||
} | ||
println("Success") | ||
} |