Sinthetized HW with input filter in the Sync signal

FPGA_Developments/Signal_Filter_Latch/Development/.library_mapping.xml

@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<com.sigasi.hdt.shared.librarymapping.model:LibraryMappings xmlns:com.sigasi.hdt.shared.librarymapping.model="com.sigasi.hdt.vhdl.scoping.librarymapping" Version="2">
+  <Mappings Location="Common Libraries/IEEE" Library="ieee"/>
+  <Mappings Location="Common Libraries/IEEE Synopsys" Library="ieee"/>
+  <Mappings Location="Common Libraries" Library="not mapped"/>
+  <Mappings Location="Common Libraries/STD" Library="std"/>
+  <Mappings Location="" Library="work"/>
+</com.sigasi.hdt.shared.librarymapping.model:LibraryMappings>

FPGA_Developments/Signal_Filter_Latch/Development/.project

@@ -0,0 +1,45 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>Signal_Filter_Latch</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.sigasi.hdt.vhdl.ui.vhdlNature</nature>
+		<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Common Libraries</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt</name>
+			<type>1</type>
+			<locationURI>sigasiresource:/vhdl/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>Common Libraries/IEEE</name>
+			<type>2</type>
+			<locationURI>sigasiresource:/vhdl/93/IEEE</locationURI>
+		</link>
+		<link>
+			<name>Common Libraries/IEEE Synopsys</name>
+			<type>2</type>
+			<locationURI>sigasiresource:/vhdl/93/IEEE%20Synopsys</locationURI>
+		</link>
+		<link>
+			<name>Common Libraries/STD</name>
+			<type>2</type>
+			<locationURI>sigasiresource:/vhdl/93/STD</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>

FPGA_Developments/Signal_Filter_Latch/Development/.settings/com.sigasi.hdt.vhdl.version.prefs

@@ -0,0 +1 @@
+<project>=93

FPGA_Developments/Signal_Filter_Latch/Development/.settings/org.eclipse.core.resources.prefs

@@ -0,0 +1,5 @@
+eclipse.preferences.version=1
+encoding//Common\ Libraries/IEEE=UTF-8
+encoding//Common\ Libraries/IEEE\ Synopsys=UTF-8
+encoding//Common\ Libraries/STD=UTF-8
+encoding/Common\ Libraries=utf-8

FPGA_Developments/Signal_Filter_Latch/Development/GenerateFilesDir.bat

@@ -0,0 +1,19 @@
+@ECHO OFF
+PUSHD "%~dp0"
+
+REM Nome do arquivo gerado
+SET FILESDIR_NAME=FilesDir.txt
+
+ECHO   Geracao inciada...
+
+REM Renomeia arquivo com timestamp
+SET FILESDIR_DATE=%date%%time%
+SET FILESDIR_DATE=%FILESDIR_DATE:/=%
+SET FILESDIR_DATE=%FILESDIR_DATE::=%
+SET FILESDIR_DATE=%FILESDIR_DATE:,=%
+SET FILESDIR_DATE=%FILESDIR_DATE: =%
+SET FILESDIR_DATE=%FILESDIR_DATE%_%FILESDIR_NAME%
+DIR ".\" /B /S /A:-D > "%FILESDIR_DATE%"
+
+ECHO   Geracao terminada!!
+REM PAUSE

FPGA_Developments/Signal_Filter_Latch/Development/Signal_Filter_Latch/sgfl_signal_filter_latch_top.vhd

@@ -0,0 +1,108 @@
+-- farm_rmap_memory_ffee_aeb_area_top.vhd
+
+-- This file was auto-generated as a prototype implementation of a module
+-- created in component editor.  It ties off all outputs to ground and
+-- ignores all inputs.  It needs to be edited to make it do something
+-- useful.
+-- 
+-- This file will not be automatically regenerated.  You should check it in
+-- to your version control system if you want to keep it.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity sgfl_signal_filter_latch_top is
+    port(
+        reset_i          : in  std_logic := '0'; --                 reset_sink.reset
+        clk_50_i         : in  std_logic := '0'; --          clock_sink_500mhz.clk
+        clk_200_i        : in  std_logic := '0'; --          clock_sink_100mhz.clk
+        unfiltered_sig_i : in  std_logic := '0'; -- conduit_end_unfiltered_sig.unfiltered_sig_signal
+        filtered_sig_o   : out std_logic ---     --   conduit_end_filtered_sig.filtered_sig_signal
+    );
+end entity sgfl_signal_filter_latch_top;
+
+architecture rtl of sgfl_signal_filter_latch_top is
+
+    -- alias --
+    alias a_sampling_clock is clk_200_i;
+    alias a_filtered_clock is clk_50_i;
+    alias a_reset is reset_i;
+
+    -- constants --
+
+    -- filter contants
+    constant c_FILTER_SIZE  : natural range 0 to 32                          := 8;
+    constant c_STABLE_CLEAR : std_logic_vector((c_FILTER_SIZE - 1) downto 0) := (others => '0');
+    constant c_STABLE_SET   : std_logic_vector((c_FILTER_SIZE - 1) downto 0) := (others => '1');
+
+    -- signals --
+
+    -- unfiltered signals (200 MHz)
+    signal s_unfiltered_sig_samples_200 : std_logic_vector((c_FILTER_SIZE - 1) downto 0);
+
+    -- filtered signals (200 MHz)
+    signal s_filtered_sig_200 : std_logic;
+
+    -- filtered signals (50 MHz)
+    signal s_filtered_sig_stage1_50 : std_logic;
+    signal s_filtered_sig_stage2_50 : std_logic;
+
+begin
+
+    -- Processes --
+
+    -- Signal Filter Latch (200 MHz) Process
+    p_sgfl_signal_filter_latch_200 : process(a_sampling_clock, a_reset) is
+    begin
+        if (a_reset = '1') then
+            -- reset signals
+            s_unfiltered_sig_samples_200 <= c_STABLE_CLEAR;
+            s_filtered_sig_200           <= '0';
+        elsif (rising_edge(a_sampling_clock)) then
+
+            -- update the unfiltered signal samples vector
+            s_unfiltered_sig_samples_200(0) <= unfiltered_sig_i;
+            for index in 1 to (c_FILTER_SIZE - 1) loop
+                s_unfiltered_sig_samples_200(index) <= s_unfiltered_sig_samples_200(index - 1);
+            end loop;
+
+            -- check if the signal is stable and clear
+            if (s_unfiltered_sig_samples_200 = c_STABLE_CLEAR) then
+                -- the signal is stable and clear
+                -- clear the filtered signal
+                s_filtered_sig_200 <= '0';
+            -- check if the signal is stable and set
+            elsif (s_unfiltered_sig_samples_200 = c_STABLE_SET) then
+                -- the signal is stable and set
+                -- set the filtered signal
+                s_filtered_sig_200 <= '1';
+            else
+                -- the signal is not stable
+                -- keep the last state
+                s_filtered_sig_200 <= s_filtered_sig_200;
+            end if;
+
+        end if;
+    end process p_sgfl_signal_filter_latch_200;
+
+    -- Signal Filter Latch (50 MHz) Process
+    p_sgfl_signal_filter_latch_50 : process(a_filtered_clock, a_reset) is
+    begin
+        if (a_reset = '1') then
+            s_filtered_sig_stage1_50 <= '0';
+            s_filtered_sig_stage2_50 <= '0';
+            filtered_sig_o           <= '0';
+        elsif (rising_edge(a_filtered_clock)) then
+
+            -- get the filtered signal with 2 stage synchronization
+            s_filtered_sig_stage1_50 <= s_filtered_sig_200;
+            s_filtered_sig_stage2_50 <= s_filtered_sig_stage1_50;
+            filtered_sig_o           <= s_filtered_sig_stage2_50;
+
+        end if;
+    end process p_sgfl_signal_filter_latch_50;
+
+    -- Signals Assignments --
+
+end architecture rtl;                   -- of sgfl_signal_filter_latch_top

FPGA_Developments/Signal_Filter_Latch/Development/Signal_Filter_Latch_hw.tcl

@@ -0,0 +1,132 @@
+# TCL File Generated by Component Editor 18.1
+# Sat Apr 04 23:17:08 BRT 2020
+# DO NOT MODIFY
+
+
+# 
+# Signal_Filter_Latch "Signal_Filter_Latch" v1.0
+# rfranca 2020.04.04.23:17:08
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module Signal_Filter_Latch
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME Signal_Filter_Latch
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR rfranca
+set_module_property DISPLAY_NAME Signal_Filter_Latch
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL sgfl_signal_filter_latch_top
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file sgfl_signal_filter_latch_top.vhd VHDL PATH Signal_Filter_Latch/sgfl_signal_filter_latch_top.vhd TOP_LEVEL_FILE
+
+add_fileset SIM_VHDL SIM_VHDL "" ""
+set_fileset_property SIM_VHDL TOP_LEVEL sgfl_signal_filter_latch_top
+set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file sgfl_signal_filter_latch_top.vhd VHDL PATH Signal_Filter_Latch/sgfl_signal_filter_latch_top.vhd TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clock_sink_50mhz
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink reset_i reset Input 1
+
+
+# 
+# connection point clock_sink_50mhz
+# 
+add_interface clock_sink_50mhz clock end
+set_interface_property clock_sink_50mhz clockRate 50000000
+set_interface_property clock_sink_50mhz ENABLED true
+set_interface_property clock_sink_50mhz EXPORT_OF ""
+set_interface_property clock_sink_50mhz PORT_NAME_MAP ""
+set_interface_property clock_sink_50mhz CMSIS_SVD_VARIABLES ""
+set_interface_property clock_sink_50mhz SVD_ADDRESS_GROUP ""
+
+add_interface_port clock_sink_50mhz clk_50_i clk Input 1
+
+
+# 
+# connection point clock_sink_200mhz
+# 
+add_interface clock_sink_200mhz clock end
+set_interface_property clock_sink_200mhz clockRate 200000000
+set_interface_property clock_sink_200mhz ENABLED true
+set_interface_property clock_sink_200mhz EXPORT_OF ""
+set_interface_property clock_sink_200mhz PORT_NAME_MAP ""
+set_interface_property clock_sink_200mhz CMSIS_SVD_VARIABLES ""
+set_interface_property clock_sink_200mhz SVD_ADDRESS_GROUP ""
+
+add_interface_port clock_sink_200mhz clk_200_i clk Input 1
+
+
+# 
+# connection point conduit_end_unfiltered_sig
+# 
+add_interface conduit_end_unfiltered_sig conduit end
+set_interface_property conduit_end_unfiltered_sig associatedClock clock_sink_200mhz
+set_interface_property conduit_end_unfiltered_sig associatedReset reset_sink
+set_interface_property conduit_end_unfiltered_sig ENABLED true
+set_interface_property conduit_end_unfiltered_sig EXPORT_OF ""
+set_interface_property conduit_end_unfiltered_sig PORT_NAME_MAP ""
+set_interface_property conduit_end_unfiltered_sig CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_end_unfiltered_sig SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_end_unfiltered_sig unfiltered_sig_i unfiltered_sig_signal Input 1
+
+
+# 
+# connection point conduit_end_filtered_sig
+# 
+add_interface conduit_end_filtered_sig conduit end
+set_interface_property conduit_end_filtered_sig associatedClock clock_sink_50mhz
+set_interface_property conduit_end_filtered_sig associatedReset reset_sink
+set_interface_property conduit_end_filtered_sig ENABLED true
+set_interface_property conduit_end_filtered_sig EXPORT_OF ""
+set_interface_property conduit_end_filtered_sig PORT_NAME_MAP ""
+set_interface_property conduit_end_filtered_sig CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_end_filtered_sig SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_end_filtered_sig filtered_sig_o filtered_sig_signal Output 1
+

FPGA_Developments/Signal_Filter_Latch/Development/Testbench/Signal_Filter_Latch_tb.cr.mti

@@ -0,0 +1,20 @@
+../Testbench/testbench_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development_DLR2/FPGA_Developments/Signal_Filter_Latch/Development/Testbench/testbench_top.vhd
+Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity testbench_top
+-- Compiling architecture RTL of testbench_top
+-- Loading entity sgfl_signal_filter_latch_top
+
+} {} {}} ../Signal_Filter_Latch/sgfl_signal_filter_latch_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development_DLR2/FPGA_Developments/Signal_Filter_Latch/Development/Signal_Filter_Latch/sgfl_signal_filter_latch_top.vhd
+Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity sgfl_signal_filter_latch_top
+-- Compiling architecture rtl of sgfl_signal_filter_latch_top
+
+} {} {}}