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plat-stm32mp1: remove unused stm32mp_nsec_can_access_reset()
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Remove unused platform functions stm32mp_nsec_can_access_reset()
and stm32mp_gpio_bank_is_non_secure().

Signed-off-by: Etienne Carriere <[email protected]>
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etienne-lms committed Nov 6, 2024
1 parent cba2930 commit 1c06e65
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Showing 2 changed files with 0 additions and 72 deletions.
59 changes: 0 additions & 59 deletions core/arch/arm/plat-stm32mp1/shared_resources.c
Original file line number Diff line number Diff line change
Expand Up @@ -437,65 +437,6 @@ bool stm32mp_periph_is_secure(enum stm32mp_shres id)
return shres_state[id] == SHRES_SECURE;
}

bool stm32mp_gpio_bank_is_non_secure(unsigned int bank)
{
unsigned int not_secure = 0;
unsigned int pin = 0;

lock_registering();

if (bank != GPIO_BANK_Z)
return true;

for (pin = 0; pin < get_gpioz_nbpin(); pin++)
if (!stm32mp_periph_is_secure(STM32MP1_SHRES_GPIOZ(pin)))
not_secure++;

return not_secure > 0 && not_secure == get_gpioz_nbpin();
}

bool stm32mp_nsec_can_access_reset(unsigned int reset_id)
{
enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT;

switch (reset_id) {
case GPIOZ_R:
return stm32mp_gpio_bank_is_non_secure(GPIO_BANK_Z);
case SPI6_R:
shres_id = STM32MP1_SHRES_SPI6;
break;
case I2C4_R:
shres_id = STM32MP1_SHRES_I2C4;
break;
case I2C6_R:
shres_id = STM32MP1_SHRES_I2C6;
break;
case USART1_R:
shres_id = STM32MP1_SHRES_USART1;
break;
case CRYP1_R:
shres_id = STM32MP1_SHRES_CRYP1;
break;
case HASH1_R:
shres_id = STM32MP1_SHRES_HASH1;
break;
case RNG1_R:
shres_id = STM32MP1_SHRES_RNG1;
break;
case MDMA_R:
shres_id = STM32MP1_SHRES_MDMA;
break;
case MCU_R:
case MCU_HOLD_BOOT_R:
shres_id = STM32MP1_SHRES_MCU;
break;
default:
return false;
}

return !stm32mp_periph_is_secure(shres_id);
}

static bool mckprot_resource(enum stm32mp_shres id)
{
switch (id) {
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13 changes: 0 additions & 13 deletions core/arch/arm/plat-stm32mp1/stm32_util.h
Original file line number Diff line number Diff line change
Expand Up @@ -58,16 +58,6 @@ static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused)
}
#endif

#ifdef CFG_STM32MP1_SHARED_RESOURCES
/* Return true if and only if @reset_id relates to a non-secure peripheral */
bool stm32mp_nsec_can_access_reset(unsigned int reset_id);
#else /* CFG_STM32MP1_SHARED_RESOURCES */
static inline bool stm32mp_nsec_can_access_reset(unsigned int reset_id __unused)
{
return true;
}
#endif /* CFG_STM32MP1_SHARED_RESOURCES */

/* Return rstctrl instance related to RCC reset controller DT binding ID */
struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id);

Expand Down Expand Up @@ -243,9 +233,6 @@ void stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl);
/* Return true if and only if resource @id is registered as secure */
bool stm32mp_periph_is_secure(enum stm32mp_shres id);

/* Return true if and only if GPIO bank @bank is registered as non-secure */
bool stm32mp_gpio_bank_is_non_secure(unsigned int bank);

/* Register parent clocks of @clock (ID used in clock DT bindings) as secure */
void stm32mp_register_clock_parents_secure(unsigned long clock_id);

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