Skip to content

Commit

Permalink
plat-stm32mp1: shared_resources: remove pin/GPIO secure state management
Browse files Browse the repository at this point in the history 
Remove the pin and GPIO secure state management from shared_resources
platform driver since this is now managed using the firewall framework.

Signed-off-by: Etienne Carriere <[email protected]>
  • Loading branch information
@etienne-lms
etienne-lms committed Nov 4, 2024
1 parent d68bb77 commit 523c9ca
Show file tree
Hide file tree
Showing 3 changed files with 5 additions and 219 deletions.
150 changes: 5 additions & 145 deletions core/arch/arm/plat-stm32mp1/shared_resources.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -132,25 +132,6 @@ static __maybe_unused const char *shres2str_state(enum shres_state id)
return shres2str_state_tbl[id];
}

/* GPIOZ bank pin count depends on SoC variants */
/* A light count routine for unpaged context to not depend on DTB support */
static int gpioz_nbpin = -1;

static unsigned int get_gpioz_nbpin(void)
{
if (gpioz_nbpin < 0)
panic();

return gpioz_nbpin;
}

void stm32mp_register_gpioz_pin_count(size_t count)
{
assert(gpioz_nbpin == -1);

gpioz_nbpin = count;
}

static void register_periph(enum stm32mp_shres id, enum shres_state state)
{
assert(id < STM32MP1_SHRES_COUNT &&
Expand Down Expand Up @@ -181,11 +162,7 @@ static void register_periph(enum stm32mp_shres id, enum shres_state state)
case STM32MP1_SHRES_GPIOZ(5):
case STM32MP1_SHRES_GPIOZ(6):
case STM32MP1_SHRES_GPIOZ(7):
if ((id - STM32MP1_SHRES_GPIOZ(0)) >= get_gpioz_nbpin()) {
EMSG("Invalid GPIO %u >= %u",
id - STM32MP1_SHRES_GPIOZ(0), get_gpioz_nbpin());
panic();
}
panic("Deprecated registering of GPIOz resources");
break;
default:
break;
Expand All @@ -196,16 +173,6 @@ static void register_periph(enum stm32mp_shres id, enum shres_state state)
/* Explore clock tree to lock secure clock dependencies */
if (state == SHRES_SECURE) {
switch (id) {
case STM32MP1_SHRES_GPIOZ(0):
case STM32MP1_SHRES_GPIOZ(1):
case STM32MP1_SHRES_GPIOZ(2):
case STM32MP1_SHRES_GPIOZ(3):
case STM32MP1_SHRES_GPIOZ(4):
case STM32MP1_SHRES_GPIOZ(5):
case STM32MP1_SHRES_GPIOZ(6):
case STM32MP1_SHRES_GPIOZ(7):
stm32mp_register_clock_parents_secure(GPIOZ);
break;
case STM32MP1_SHRES_IWDG1:
stm32mp_register_clock_parents_secure(IWDG1);
break;
Expand Down Expand Up @@ -310,7 +277,8 @@ static void register_periph_iomem(vaddr_t base, enum shres_state state)
case GPIOI_BASE:
case GPIOJ_BASE:
case GPIOK_BASE:
fallthrough;
panic("Deprecated registering of GPIOz resources");
break;
#endif
#ifdef CFG_WITH_NSEC_UARTS
case USART2_BASE:
Expand Down Expand Up @@ -352,80 +320,6 @@ void stm32mp_register_non_secure_periph_iomem(vaddr_t base)
register_periph_iomem(base, SHRES_NON_SECURE);
}

/* Register GPIO resource */
void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin)
{
switch (bank) {
case GPIO_BANK_Z:
assert(pin < get_gpioz_nbpin());
register_periph(STM32MP1_SHRES_GPIOZ(pin), SHRES_SECURE);
break;
default:
EMSG("GPIO bank %u cannot be secured", bank);
panic();
}
}

void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin)
{
switch (bank) {
case GPIO_BANK_Z:
assert(pin < get_gpioz_nbpin());
register_periph(STM32MP1_SHRES_GPIOZ(pin), SHRES_NON_SECURE);
break;
default:
break;
}
}

void stm32mp_register_secure_pinctrl(struct pinctrl_state *pinctrl)
{
unsigned int *bank = NULL;
unsigned int *pin = NULL;
size_t count = 0;
size_t n = 0;

stm32_gpio_pinctrl_bank_pin(pinctrl, NULL, NULL, &count);
if (!count)
return;

bank = calloc(count, sizeof(*bank));
pin = calloc(count, sizeof(*pin));
if (!bank || !pin)
panic();

stm32_gpio_pinctrl_bank_pin(pinctrl, bank, pin, &count);
for (n = 0; n < count; n++)
stm32mp_register_secure_gpio(bank[n], pin[n]);

free(bank);
free(pin);
}

void stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl)
{
unsigned int *bank = NULL;
unsigned int *pin = NULL;
size_t count = 0;
size_t n = 0;

stm32_gpio_pinctrl_bank_pin(pinctrl, NULL, NULL, &count);
if (!count)
return;

bank = calloc(count, sizeof(*bank));
pin = calloc(count, sizeof(*pin));
if (!bank || !pin)
panic();

stm32_gpio_pinctrl_bank_pin(pinctrl, bank, pin, &count);
for (n = 0; n < count; n++)
stm32mp_register_non_secure_gpio(bank[n], pin[n]);

free(bank);
free(pin);
}

static void lock_registering(void)
{
registering_locked = true;
Expand All @@ -438,40 +332,6 @@ bool stm32mp_periph_is_secure(enum stm32mp_shres id)
return shres_state[id] == SHRES_SECURE;
}

bool stm32mp_gpio_bank_is_non_secure(unsigned int bank)
{
unsigned int not_secure = 0;
unsigned int pin = 0;

lock_registering();

if (bank != GPIO_BANK_Z)
return true;

for (pin = 0; pin < get_gpioz_nbpin(); pin++)
if (!stm32mp_periph_is_secure(STM32MP1_SHRES_GPIOZ(pin)))
not_secure++;

return not_secure > 0 && not_secure == get_gpioz_nbpin();
}

bool stm32mp_gpio_bank_is_secure(unsigned int bank)
{
unsigned int secure = 0;
unsigned int pin = 0;

lock_registering();

if (bank != GPIO_BANK_Z)
return false;

for (pin = 0; pin < get_gpioz_nbpin(); pin++)
if (stm32mp_periph_is_secure(STM32MP1_SHRES_GPIOZ(pin)))
secure++;

return secure > 0 && secure == get_gpioz_nbpin();
}

bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
{
enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT;
Expand Down Expand Up @@ -503,7 +363,7 @@ bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
case BSEC:
return true;
case GPIOZ:
return !stm32mp_gpio_bank_is_secure(GPIO_BANK_Z);
return true;
case SPI6_K:
shres_id = STM32MP1_SHRES_SPI6;
break;
Expand Down Expand Up @@ -547,7 +407,7 @@ bool stm32mp_nsec_can_access_reset(unsigned int reset_id)

switch (reset_id) {
case GPIOZ_R:
return stm32mp_gpio_bank_is_non_secure(GPIO_BANK_Z);
return false;
case SPI6_R:
shres_id = STM32MP1_SHRES_SPI6;
break;
Expand Down
71 changes: 0 additions & 71 deletions core/arch/arm/plat-stm32mp1/stm32_util.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -221,49 +221,12 @@ void stm32mp_register_secure_periph_iomem(vaddr_t base);
*/
void stm32mp_register_non_secure_periph_iomem(vaddr_t base);

/*
* Register GPIO resource as a secure peripheral
* @bank: Bank of the target GPIO
* @pin: Bit position of the target GPIO in the bank
*/
void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin);

/*
* Register GPIO resource as a non-secure peripheral
* @bank: Bank of the target GPIO
* @pin: Bit position of the target GPIO in the bank
*/
void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin);

/*
* Register pin resource of a pin control state as a secure peripheral
* @bank: Bank of the target GPIO
* @pin: Bit position of the target GPIO in the bank
*/
void stm32mp_register_secure_pinctrl(struct pinctrl_state *pinctrl);

/*
* Register pin resource of a pin control state as a non-secure peripheral
* @bank: Bank of the target GPIO
* @pin: Bit position of the target GPIO in the bank
*/
void stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl);

/* Return true if and only if resource @id is registered as secure */
bool stm32mp_periph_is_secure(enum stm32mp_shres id);

/* Return true if and only if GPIO bank @bank is registered as secure */
bool stm32mp_gpio_bank_is_secure(unsigned int bank);

/* Return true if and only if GPIO bank @bank is registered as non-secure */
bool stm32mp_gpio_bank_is_non_secure(unsigned int bank);

/* Register parent clocks of @clock (ID used in clock DT bindings) as secure */
void stm32mp_register_clock_parents_secure(unsigned long clock_id);

/* Register number of pins in the GPIOZ bank */
void stm32mp_register_gpioz_pin_count(size_t count);

#else /* CFG_STM32MP1_SHARED_RESOURCES */

static inline void stm32mp_register_secure_periph(enum stm32mp_shres id
Expand All @@ -285,48 +248,14 @@ static inline void stm32mp_register_non_secure_periph_iomem(vaddr_t base
{
}

static inline void stm32mp_register_secure_gpio(unsigned int bank __unused,
unsigned int pin __unused)
{
}

static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused,
unsigned int pin __unused)
{
}

static inline void
stm32mp_register_secure_pinctrl(struct pinctrl_state *pinctrl __unused)
{
}

static inline void
stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl __unused)
{
}

static inline bool stm32mp_periph_is_secure(enum stm32mp_shres id __unused)
{
return true;
}

static inline bool stm32mp_gpio_bank_is_secure(unsigned int bank __unused)
{
return true;
}

static inline bool stm32mp_gpio_bank_is_non_secure(unsigned int bank __unused)
{
return false;
}

static inline void stm32mp_register_clock_parents_secure(unsigned long clock_id
__unused)
{
}

static inline void stm32mp_register_gpioz_pin_count(size_t count __unused)
{
}
#endif /* CFG_STM32MP1_SHARED_RESOURCES */
#endif /*__STM32_UTIL_H__*/
3 changes: 0 additions & 3 deletions core/drivers/stm32_gpio.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1186,9 +1186,6 @@ static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node,
bank->base = io_pa_or_va_nsec(&pa_va, blen);
}

if (compat->gpioz)
stm32mp_register_gpioz_pin_count(bank->ngpios);

*out_bank = bank;

return TEE_SUCCESS;
Expand Down

0 comments on commit 523c9ca

Please sign in to comment.