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core: stm32_gpio: register firewall controllers for GPIO access rights #7102

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merged 20 commits into from
Dec 6, 2024
Merged

core: stm32_gpio: register firewall controllers for GPIO access rights #7102

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1f0fed5
dt-bindings: gpio: stm32mp: flags for non-secure GPIOs
etienne-lms Jul 4, 2024
c80834b
dt-bindings: pinctrl: stm32mp: flags for non-secure pins
etienne-lms Sep 17, 2024
a229b2a
dts: stm32: define SoC GPIO banks that are firewall controllers
etienne-lms Sep 2, 2024
affbb39
dts: stm32: most stm32mp15 UARTs pinctrl are non-secure
etienne-lms Jul 19, 2024
0863009
dts: stm32: refine STM32MP15 secure/non-secure I2C4 pinctrl states
etienne-lms Sep 16, 2024
ba913d5
dts: stm32: refine STM32MP13 secure/non-secure USART4 pinctrl states
etienne-lms Sep 17, 2024
a78abea
dts: stm32: refine STM32MP25 secure/non-secure USART2 pinctrl states
etienne-lms Sep 17, 2024
37541a9
drivers: stm32_gpio: check GPIO is not already consumed
etienne-lms Jul 19, 2024
8625e4a
drivers: stm32_gpio: factorize apply_rif_config()
etienne-lms Sep 2, 2024
6007d0f
drivers: stm32_gpio: register to firewall framework
etienne-lms Sep 2, 2024
1d8bbf9
drivers: stm32_gpio: acquire semaphore when GPIO/pinctrl are used
etienne-lms Jul 19, 2024
8d5854f
drivers: stm32_gpio: check secure state of consumed GPIOs
etienne-lms Dec 5, 2024
bd976d6
drivers: stm32_gpio: check secure state of pinctrl states
etienne-lms Oct 23, 2024
512faf9
plat-stm32mp1: shared_resources: do not manage pins secure state
etienne-lms Oct 23, 2024
9874822
drivers: stm32_i2c: remove use of stm32_pinctrl_set_secure_cfg()
etienne-lms Oct 23, 2024
3f69815
drivers: stm32_uart: remove use of stm32_pinctrl_set_secure_cfg()
etienne-lms Oct 23, 2024
83bf7e3
drivers: stm32_uart: remove use of shared_resource for pinctlr
etienne-lms Oct 23, 2024
cb731cf
plat-stm32mp1: stm32mp1_stpmic: remove use of shared_resource for pin…
etienne-lms Oct 23, 2024
ec8b8d6
drivers: stm32_gpio: remove gpio/pinctrl API function to set secure s…
etienne-lms Jul 4, 2024
b2a5f61
plat-stm32mp1: shared_resources: remove pin/GPIO secure state management
etienne-lms Oct 23, 2024
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4 changes: 2 additions & 2 deletions core/arch/arm/dts/stm32mp13-pinctrl.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -27,13 +27,13 @@

uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
pinmux = <STM32_PINMUX_NSEC('D', 6, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
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};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
pinmux = <STM32_PINMUX_NSEC('D', 8, AF8)>; /* UART4_RX */
bias-disable;
};
};
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9 changes: 9 additions & 0 deletions core/arch/arm/dts/stm32mp131.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -291,6 +291,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#access-controller-cells = <1>;
clocks = <&rcc GPIOA>;
reg = <0x0 0x400>;
st,bank-name = "GPIOA";
Expand All @@ -303,6 +304,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#access-controller-cells = <1>;
clocks = <&rcc GPIOB>;
reg = <0x1000 0x400>;
st,bank-name = "GPIOB";
Expand All @@ -315,6 +317,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#access-controller-cells = <1>;
clocks = <&rcc GPIOC>;
reg = <0x2000 0x400>;
st,bank-name = "GPIOC";
Expand All @@ -327,6 +330,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#access-controller-cells = <1>;
clocks = <&rcc GPIOD>;
reg = <0x3000 0x400>;
st,bank-name = "GPIOD";
Expand All @@ -339,6 +343,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#access-controller-cells = <1>;
clocks = <&rcc GPIOE>;
reg = <0x4000 0x400>;
st,bank-name = "GPIOE";
Expand All @@ -351,6 +356,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#access-controller-cells = <1>;
clocks = <&rcc GPIOF>;
reg = <0x5000 0x400>;
st,bank-name = "GPIOF";
Expand All @@ -363,6 +369,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#access-controller-cells = <1>;
clocks = <&rcc GPIOG>;
reg = <0x6000 0x400>;
st,bank-name = "GPIOG";
Expand All @@ -375,6 +382,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#access-controller-cells = <1>;
clocks = <&rcc GPIOH>;
reg = <0x7000 0x400>;
st,bank-name = "GPIOH";
Expand All @@ -387,6 +395,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#access-controller-cells = <1>;
clocks = <&rcc GPIOI>;
reg = <0x8000 0x400>;
st,bank-name = "GPIOI";
Expand Down
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