drivers: sam: update PLL ready time, add driver for pit64b #7103
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etienne-lms
reviewed
Nov 5, 2024
core/drivers/microchip_pit.c
Outdated
| #include <drivers/clk_dt.h> | ||
| #include <string.h> | ||
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| #define MCHP_PIT64B_FREQ 5000000UL /* 5 MHz */ |
| break; | ||
| } | ||
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| if (!parent) |
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| res = clk_dt_get_by_name(fdt, node, "gclk", &gclk); | ||
| if (res) | ||
| return res; |
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For consistency, I suggest to get the clock first, then to act on clocks:
res = clk_dt_get_by_name(fdt, node, "pclk", &pclk);
if (res)
return res;
- res = clk_enable(pclk);
- if (res)
- panic();
-
res = clk_dt_get_by_name(fdt, node, "gclk", &gclk);
if (res)
return res;
+ res = clk_enable(pclk);
+ if (res)
+ panic();
+| #include <assert.h> | ||
| #include <drivers/clk.h> | ||
| #include <drivers/clk_dt.h> | ||
| #include <string.h> |
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TonyHan11
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@etienne-lms updated according to the comments, thank you very much. |
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This pull request has been marked as a stale pull request because it has been open (more than) 30 days with no activity. Remove the stale label or add a comment, otherwise this pull request will automatically be closed in 5 days. Note, that you can always re-open a closed issue at any time. |
TonyHan11
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The start-up time (simulation data) of sama7g5 PLL is 50us in condition reaching 95% of target frequency. The PLL lock status bit is not set a few times with current timeout setting. Extend the time to make sure the check is successful for any cases. Signed-off-by: Tony Han <[email protected]>
Add support for the peripheral PIT64B in sama7g54. In the driver the clocks are initialized for PIT64B. Signed-off-by: Tony Han <[email protected]>
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rebsed on the master branch. |
etienne-lms
reviewed
Dec 9, 2024
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