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plat-stm32mp1: remove registering to platform shared_resources driver #7169

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plat-stm32mp1: remove registering to platform shared_resources driver #7169

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a3bf66c
plat-stm32mp1: CFG_STM32_IWDG requires CFG_WDT_SM_HANDLER
etienne-lms Dec 10, 2024
4c866bd
drivers: stm32_iwdg: remove registering to shared_resources driver
etienne-lms Oct 22, 2024
682e76d
drivers: stm32_iwdg: remove useless device list
etienne-lms Dec 9, 2024
90c751c
drivers: stm32_rng: remove registering to shared_resources driver
etienne-lms Oct 22, 2024
695512d
drivers: stm32_uart: remove registering to shared_resources driver
etienne-lms Oct 22, 2024
3d706ce
drivers: stm32_cryp: remove registering to shared_resource driver
etienne-lms Oct 22, 2024
0df1333
plat-stm32mp1: remove PMIC registering to shared_resources driver
etienne-lms Dec 9, 2024
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1 change: 1 addition & 0 deletions core/arch/arm/plat-stm32mp1/conf.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -270,6 +270,7 @@ $(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL))
CFG_WDT ?= $(CFG_STM32_IWDG)
CFG_WDT_SM_HANDLER ?= $(CFG_WDT)
CFG_WDT_SM_HANDLER_ID ?= 0xbc000000
$(eval $(call cfg-depends-all,CFG_STM32_IWDG,CFG_WDT_SM_HANDLER CFG_WDT))

# Platform specific configuration
CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y
Expand Down
19 changes: 1 addition & 18 deletions core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c
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Expand Up @@ -670,21 +670,6 @@ void stm32mp_put_pmic(void)
stm32_i2c_suspend(i2c_handle);
}

static void register_non_secure_pmic(void)
{
/* Allow this function to be called when STPMIC1 not used */
if (!i2c_handle->base.pa)
return;

stm32mp_register_non_secure_periph_iomem(i2c_handle->base.pa);
}

static void register_secure_pmic(void)
{
stm32mp_register_secure_periph_iomem(i2c_handle->base.pa);
register_pm_driver_cb(pmic_pm, NULL, "stm32mp1-pmic");
}

static TEE_Result initialize_pmic(const void *fdt, int pmic_node)
{
unsigned long pmic_version = 0;
Expand All @@ -702,9 +687,7 @@ static TEE_Result initialize_pmic(const void *fdt, int pmic_node)
stm32mp_put_pmic();

if (dt_pmic_is_secure())
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I don't fancy we rely of secure-status in dt_pmic_is_secure()

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We can address this in a dedicated P-R, it's out of the scope of this series that only intend to get rid of plat-stm32mp1/shared_resources.c.

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I've created #7172 to address that point.

register_secure_pmic();
else
register_non_secure_pmic();
register_pm_driver_cb(pmic_pm, NULL, "stm32mp1-pmic");

parse_regulator_fdt_nodes(fdt, pmic_node);

Expand Down
20 changes: 9 additions & 11 deletions core/arch/arm/plat-stm32mp1/main.c
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Expand Up @@ -86,17 +86,16 @@ void plat_console_init(void)
/* Early console initialization before MMU setup */
struct uart {
paddr_t pa;
bool secure;
} uarts[] = {
[0] = { .pa = 0 },
[1] = { .pa = USART1_BASE, .secure = true, },
[2] = { .pa = USART2_BASE, .secure = false, },
[3] = { .pa = USART3_BASE, .secure = false, },
[4] = { .pa = UART4_BASE, .secure = false, },
[5] = { .pa = UART5_BASE, .secure = false, },
[6] = { .pa = USART6_BASE, .secure = false, },
[7] = { .pa = UART7_BASE, .secure = false, },
[8] = { .pa = UART8_BASE, .secure = false, },
[1] = { .pa = USART1_BASE },
[2] = { .pa = USART2_BASE },
[3] = { .pa = USART3_BASE },
[4] = { .pa = UART4_BASE },
[5] = { .pa = UART5_BASE },
[6] = { .pa = USART6_BASE },
[7] = { .pa = UART7_BASE },
[8] = { .pa = UART8_BASE },
};

COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART);
Expand All @@ -107,7 +106,6 @@ void plat_console_init(void)
/* No clock yet bound to the UART console */
console_data.clock = NULL;

console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure;
stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa);

register_serial_console(&console_data.chip);
Expand Down Expand Up @@ -144,7 +142,7 @@ static TEE_Result init_console_from_dt(void)
console_flush();
console_data = *pd;
register_serial_console(&console_data.chip);
IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-");
IMSG("DTB enables console");
free(pd);

return TEE_SUCCESS;
Expand Down
22 changes: 10 additions & 12 deletions core/arch/arm/plat-stm32mp2/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -65,18 +65,17 @@ void plat_console_init(void)
/* Early console initialization before MMU setup */
struct uart {
paddr_t pa;
bool secure;
} uarts[] = {
[0] = { .pa = 0 },
[1] = { .pa = USART1_BASE, .secure = true, },
[2] = { .pa = USART2_BASE, .secure = false, },
[3] = { .pa = USART3_BASE, .secure = false, },
[4] = { .pa = UART4_BASE, .secure = false, },
[5] = { .pa = UART5_BASE, .secure = false, },
[6] = { .pa = USART6_BASE, .secure = false, },
[7] = { .pa = UART7_BASE, .secure = false, },
[8] = { .pa = UART8_BASE, .secure = false, },
[9] = { .pa = UART9_BASE, .secure = false, },
[1] = { .pa = USART1_BASE },
[2] = { .pa = USART2_BASE },
[3] = { .pa = USART3_BASE },
[4] = { .pa = UART4_BASE },
[5] = { .pa = UART5_BASE },
[6] = { .pa = USART6_BASE },
[7] = { .pa = UART7_BASE },
[8] = { .pa = UART8_BASE },
[9] = { .pa = UART9_BASE },
};

static_assert(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART);
Expand All @@ -86,7 +85,6 @@ void plat_console_init(void)

/* No clock yet bound to the UART console */
console_data.clock = NULL;
console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure;
stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa);
register_serial_console(&console_data.chip);

Expand Down Expand Up @@ -124,7 +122,7 @@ static TEE_Result init_console_from_dt(void)
console_flush();
console_data = *pd;
register_serial_console(&console_data.chip);
IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-");
IMSG("DTB enables console");
free(pd);

return TEE_SUCCESS;
Expand Down
2 changes: 0 additions & 2 deletions core/drivers/crypto/stm32/stm32_cryp.c
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Expand Up @@ -1296,8 +1296,6 @@ static TEE_Result stm32_cryp_probe(const void *fdt, int node,
if (!cryp_pdata.base.va)
panic();

stm32mp_register_secure_periph_iomem(cryp_pdata.base.pa);

if (clk_enable(cryp_pdata.clock))
panic();

Expand Down
62 changes: 11 additions & 51 deletions core/drivers/stm32_iwdg.c
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Expand Up @@ -61,14 +61,12 @@
* IWDG_FLAGS_HW_ENABLED Watchdog is enabled by BootROM
* IWDG_FLAGS_DISABLE_ON_STOP Watchdog is freezed in SoC STOP mode
* IWDG_FLAGS_DISABLE_ON_STANDBY Watchdog is freezed in SoC STANDBY mode
* IWDG_FLAGS_NON_SECURE Instance is assigned to non-secure world
* IWDG_FLAGS_ENABLED Watchdog has been enabled
*/
#define IWDG_FLAGS_HW_ENABLED BIT(0)
#define IWDG_FLAGS_DISABLE_ON_STOP BIT(1)
#define IWDG_FLAGS_DISABLE_ON_STANDBY BIT(2)
#define IWDG_FLAGS_NON_SECURE BIT(3)
#define IWDG_FLAGS_ENABLED BIT(4)
#define IWDG_FLAGS_ENABLED BIT(3)

/*
* IWDG watch instance data
Expand All @@ -78,7 +76,6 @@
* @flags - Property flags for the IWDG instance
* @timeout - Watchdog elaspure timeout
* @wdt_chip - Wathcdog chip instance
* @link - Link in registered watchdog instance list
*/
struct stm32_iwdg_device {
struct io_pa_va base;
Expand All @@ -87,22 +84,13 @@ struct stm32_iwdg_device {
uint32_t flags;
unsigned long timeout;
struct wdt_chip wdt_chip;
SLIST_ENTRY(stm32_iwdg_device) link;
};

static SLIST_HEAD(iwdg_dev_list_head, stm32_iwdg_device) iwdg_dev_list =
SLIST_HEAD_INITIALIZER(iwdg_dev_list_head);

static vaddr_t get_base(struct stm32_iwdg_device *iwdg)
{
return io_pa_or_va(&iwdg->base, 1);
}

static bool is_assigned_to_nsec(struct stm32_iwdg_device *iwdg)
{
return iwdg->flags & IWDG_FLAGS_NON_SECURE;
}

static void iwdg_wdt_set_enabled(struct stm32_iwdg_device *iwdg)
{
iwdg->flags |= IWDG_FLAGS_ENABLED;
Expand Down Expand Up @@ -268,17 +256,9 @@ static TEE_Result stm32_iwdg_parse_fdt(struct stm32_iwdg_device *iwdg,
if (res)
return res;

if (dt_info.status == DT_STATUS_OK_NSEC)
iwdg->flags |= IWDG_FLAGS_NON_SECURE;

/* Get IOMEM address */
iwdg->base.pa = dt_info.reg;

if (iwdg->flags & IWDG_FLAGS_NON_SECURE)
io_pa_or_va_nsec(&iwdg->base, dt_info.reg_size);
else
io_pa_or_va_secure(&iwdg->base, dt_info.reg_size);

io_pa_or_va_secure(&iwdg->base, dt_info.reg_size);
assert(iwdg->base.va);

/* Get and check timeout value */
Expand Down Expand Up @@ -355,50 +335,30 @@ static TEE_Result stm32_iwdg_setup(struct stm32_iwdg_device *iwdg,
return TEE_SUCCESS;
}

static TEE_Result stm32_iwdg_register(struct stm32_iwdg_device *iwdg)
{
TEE_Result res = TEE_ERROR_GENERIC;

if (is_assigned_to_nsec(iwdg)) {
stm32mp_register_non_secure_periph_iomem(iwdg->base.pa);
} else {
stm32mp_register_secure_periph_iomem(iwdg->base.pa);

/* Expose watchdog runtime service only to secure IWDG */
iwdg->wdt_chip.ops = &stm32_iwdg_ops;

res = watchdog_register(&iwdg->wdt_chip);
if (res)
return res;
}

SLIST_INSERT_HEAD(&iwdg_dev_list, iwdg, link);

return TEE_SUCCESS;
}

static TEE_Result stm32_iwdg_probe(const void *fdt, int node,
const void *compat_data __unused)
{
struct stm32_iwdg_device *iwdg = NULL;
TEE_Result res = TEE_SUCCESS;

static_assert(IS_ENABLED(CFG_WDT) && IS_ENABLED(CFG_WDT_SM_HANDLER));
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This is not useful as CFG_STM32_IWDG is disabled when either CFG_WDT or CFG_WDT_SM_HANDLER is disabled?


iwdg = calloc(1, sizeof(*iwdg));
if (!iwdg)
return TEE_ERROR_OUT_OF_MEMORY;

res = stm32_iwdg_setup(iwdg, fdt, node);
if (res)
goto err;
goto out;

res = stm32_iwdg_register(iwdg);
if (res)
goto err;
iwdg->wdt_chip.ops = &stm32_iwdg_ops;

return TEE_SUCCESS;
res = watchdog_register(&iwdg->wdt_chip);

out:
if (res)
free(iwdg);

err:
free(iwdg);
return res;
}

Expand Down
8 changes: 0 additions & 8 deletions core/drivers/stm32_rng.c
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Expand Up @@ -670,14 +670,6 @@ static TEE_Result stm32_rng_probe(const void *fdt, int offs,
if (res)
goto err;

#if defined(CFG_STM32MP15) && defined(CFG_STM32_ETZPC)
/* Only STM32MP15 requires a software registering of RNG secure state */
if (etzpc_get_decprot(STM32MP1_ETZPC_RNG1_ID) == ETZPC_DECPROT_NS_RW)
stm32mp_register_non_secure_periph_iomem(stm32_rng->base.pa);
else
stm32mp_register_secure_periph_iomem(stm32_rng->base.pa);
#endif /* defined(CFG_STM32MP15) && defined(CFG_STM32_ETZPC) */

/* Power management implementation expects both or none are set */
assert(stm32_rng->ddata->has_power_optim ==
stm32_rng->ddata->has_cond_reset);
Expand Down
26 changes: 2 additions & 24 deletions core/drivers/stm32_uart.c
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Expand Up @@ -109,21 +109,6 @@ void stm32_uart_init(struct stm32_uart_pdata *pd, vaddr_t base)
pd->chip.ops = &stm32_uart_serial_ops;
}

static void register_secure_uart(struct stm32_uart_pdata *pd __maybe_unused)
{
#ifndef CFG_STM32MP25
stm32mp_register_secure_periph_iomem(pd->base.pa);
#endif
}

static void register_non_secure_uart(struct stm32_uart_pdata *pd __maybe_unused)
{
#ifndef CFG_STM32MP25
stm32mp_register_non_secure_periph_iomem(pd->base.pa);
#endif

}

struct stm32_uart_pdata *stm32_uart_init_from_dt_node(void *fdt, int node)
{
TEE_Result res = TEE_ERROR_GENERIC;
Expand All @@ -144,7 +129,6 @@ struct stm32_uart_pdata *stm32_uart_init_from_dt_node(void *fdt, int node)

pd->chip.ops = &stm32_uart_serial_ops;
pd->base.pa = info.reg;
pd->secure = (info.status == DT_STATUS_OK_SEC);

res = clk_dt_get_by_index(fdt, node, 0, &pd->clock);
if (res) {
Expand All @@ -157,9 +141,8 @@ struct stm32_uart_pdata *stm32_uart_init_from_dt_node(void *fdt, int node)
panic();

assert(cpu_mmu_enabled());
pd->base.va = (vaddr_t)phys_to_virt(pd->base.pa,
pd->secure ? MEM_AREA_IO_SEC :
MEM_AREA_IO_NSEC, info.reg_size);
pd->base.va = (vaddr_t)phys_to_virt(pd->base.pa, MEM_AREA_IO_SEC,
info.reg_size);

res = pinctrl_get_state_by_name(fdt, node, "default", &pd->pinctrl);
if (res)
Expand All @@ -173,10 +156,5 @@ struct stm32_uart_pdata *stm32_uart_init_from_dt_node(void *fdt, int node)
if (res)
panic();

if (pd->secure)
register_secure_uart(pd);
else
register_non_secure_uart(pd);

return pd;
}
1 change: 0 additions & 1 deletion core/include/drivers/stm32_uart.h
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Expand Up @@ -16,7 +16,6 @@
struct stm32_uart_pdata {
struct io_pa_va base;
struct serial_chip chip;
bool secure;
struct clk *clock;
struct pinctrl_state *pinctrl;
struct pinctrl_state *pinctrl_sleep;
Expand Down
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