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Merge pull request #138 from eiln/eileen/bootloader
[READY] Bootloader Upgrade
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@@ -1,13 +1,13 @@ | ||
/** | ||
* @file bootloader_common.h | ||
* @author Adam Busch ([email protected]) | ||
* @brief Common bootloader functions for all firmware components. | ||
* @brief Common bootloader functions for all firmware components. | ||
* Useful for entering the bootloader to download new firmware | ||
* @version 0.1 | ||
* @date 2022-03-10 | ||
* | ||
* | ||
* @copyright Copyright (c) 2022 | ||
* | ||
* | ||
*/ | ||
#ifndef _BOOTLOADER_COMMON_H_ | ||
#define _BOOTLOADER_COMMON_H_ | ||
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@@ -27,7 +27,9 @@ typedef enum | |
{ | ||
BLCMD_START = 0x1, /* Request to start firmware download */ | ||
BLCMD_CRC = 0x3, /* Final CRC-32b check of firmware */ | ||
BLCMD_RST = 0x5 /* Request for reset */ | ||
BLCMD_CRC_BACKUP = 0x2, | ||
BLCMD_JUMP = 0x4, /* Request to start firmware download */ | ||
BLCMD_RST = 0x5, /* Request for reset */ | ||
} BLCmd_t; | ||
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typedef enum { | ||
|
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@@ -0,0 +1,75 @@ | ||
/** | ||
* @file crc.c | ||
* @author Eileen Yoon ([email protected]) | ||
* @brief Hardware CRC32 w/ software fallback | ||
* @version 0.1 | ||
* @date 2024-11-25 | ||
* | ||
* @copyright Copyright (c) 2024 | ||
* | ||
*/ | ||
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#include "crc.h" | ||
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void PHAL_CRC32_Reset(void) | ||
{ | ||
// CRC initializaion | ||
#if defined(STM32L496xx) || defined(STM32L432xx) || defined(STM32F732xx) | ||
RCC->AHB1ENR |= RCC_AHB1ENR_CRCEN; // Clock the CRC peripheral | ||
CRC->INIT = 0xFFFFFFFF; // Reset initial value | ||
CRC->CR &= ~CRC_CR_POLYSIZE_Msk; // Set 32 bit (00) | ||
CRC->POL = 0x04C11DB7; // CRC-32b (Ethernet Polynomial) | ||
CRC->CR |= CRC_CR_RESET; // Reset CRC | ||
#else | ||
RCC->AHB1ENR |= RCC_AHB1ENR_CRCEN; // F4 only supports CRC-32b | ||
CRC->CR = CRC_CR_RESET; | ||
#endif | ||
} | ||
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void PHAL_CRC32_Init(void) | ||
{ | ||
PHAL_CRC32_Reset(); | ||
} | ||
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uint32_t PHAL_CRC32_Calculate(uint32_t *data, uint32_t count) | ||
{ | ||
PHAL_CRC32_Reset(); | ||
__DSB(); | ||
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for (uint32_t i = 0; i < count; i++) | ||
CRC->DR = data[i]; | ||
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return CRC->DR; | ||
} | ||
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static const uint32_t crc32b_LUT[16] = { | ||
0x00000000, 0x04C11DB7, 0x09823B6E, 0x0D4326D9, | ||
0x130476DC, 0x17C56B6B, 0x1A864DB2, 0x1E475005, | ||
0x2608EDB8, 0x22C9F00F, 0x2F8AD6D6, 0x2B4BCB61, | ||
0x350C9B64, 0x31CD86D3, 0x3C8EA00A, 0x384FBDBD, | ||
}; | ||
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static inline uint32_t update_crc(uint32_t crc, uint32_t data) | ||
{ | ||
crc = crc ^ data; // Apply all 32-bits | ||
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// Process 32-bits, 4 at a time, or 8 rounds | ||
crc = (crc << 4) ^ crc32b_LUT[crc >> 28]; | ||
crc = (crc << 4) ^ crc32b_LUT[crc >> 28]; | ||
crc = (crc << 4) ^ crc32b_LUT[crc >> 28]; | ||
crc = (crc << 4) ^ crc32b_LUT[crc >> 28]; | ||
crc = (crc << 4) ^ crc32b_LUT[crc >> 28]; | ||
crc = (crc << 4) ^ crc32b_LUT[crc >> 28]; | ||
crc = (crc << 4) ^ crc32b_LUT[crc >> 28]; | ||
crc = (crc << 4) ^ crc32b_LUT[crc >> 28]; | ||
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return crc; | ||
} | ||
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uint32_t PHAL_CRC32_CalculateSW(uint32_t *data, uint32_t count) | ||
{ | ||
uint32_t crc = 0xFFFFFFFF; | ||
for (uint32_t i = 0; i < count; i++) | ||
crc = update_crc(crc, data[i]); | ||
return crc; | ||
} |
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@@ -0,0 +1,31 @@ | ||
/** | ||
* @file crc.h | ||
* @author Eileen Yoon ([email protected]) | ||
* @brief Hardware CRC32 w/ software fallback | ||
* @version 0.1 | ||
* @date 2024-11-25 | ||
* | ||
* @copyright Copyright (c) 2024 | ||
* | ||
*/ | ||
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#ifndef _PHAL_CRC_H | ||
#define _PHAL_CRC_H | ||
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#if defined(STM32F407xx) | ||
#include "stm32f4xx.h" | ||
#include "system_stm32f4xx.h" | ||
#elif defined(STM32F732xx) | ||
#include "stm32f7xx.h" | ||
#include "system_stm32f7xx.h" | ||
#else | ||
#error "Please define a MCU arch" | ||
#endif | ||
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void PHAL_CRC32_Reset(void); | ||
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uint32_t PHAL_CRC32_Calculate(uint32_t *data, uint32_t count); | ||
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uint32_t PHAL_CRC32_CalculateSW(uint32_t *data, uint32_t count); | ||
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#endif // _PHAL_CRC_H |
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