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Modify the clock rate of xspi0 in the example #23

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Dec 1, 2024
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Modify the clock rate of xspi0 in the example #23

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2 changes: 1 addition & 1 deletion projects/etherkit_basic_key_irq/.secure_xml
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Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@
<node id="board.clock.pclkl.display" option="board.clock.pclkl.display.value"/>
<node id="board.clock.pclkadc.display" option="board.clock.pclkadc.display.value"/>
<node id="board.clock.pclkcan.freq" option="board.clock.pclkcan.freq.40m"/>
<node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.12m"/>
<node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.133m"/>
<node id="board.clock.xspi.clk1.freq" option="board.clock.xspi.clk1.freq.12m"/>
<node id="board.clock.tclk.freq" option="board.clock.tclk.freq.100m"/>
</raClockConfiguration>
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4 changes: 2 additions & 2 deletions projects/etherkit_basic_key_irq/.settings/standalone.prefs
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@@ -1,4 +1,4 @@
#Wed Nov 27 16:36:04 CST 2024
#Thu Nov 28 17:26:24 CST 2024
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.0.0/all=907937621,script/fsp_xspi0_boot.icf|3822962514,rzn/board/rzn2l_rsk/board_leds.c|358444977,rzn/board/rzn2l_rsk/board_init.c|2067006575,rzn/board/rzn2l_rsk/board.h|736691883,rzn/board/rzn2l_rsk/board_ethernet_phy.h|1631979823,rzn/board/rzn2l_rsk/board_leds.h|1430483072,rzn/board/rzn2l_rsk/board_init.h
com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=
Expand All @@ -15,7 +15,7 @@ com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp_xspi0_boot.icf
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.1.fsp.2.0.0/all=1441545198,rzn/arm/CMSIS_5/LICENSE.txt|4247764709,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h|1135074086,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h|510668081,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h|4245531541,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h|1887099957,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h|3334069041,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/all=
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=PinConfiguration
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=ClockGeneration
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#2.0.0/all=3076664292,rzn/fsp/src/r_icu/r_icu.c|2881269901,rzn/fsp/inc/instances/r_icu.h|1436939059,rzn/fsp/inc/api/r_external_irq_api.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.0.0/all=2921827146,rzn/fsp/src/r_sci_uart/r_sci_uart.c|4093801030,rzn/fsp/inc/instances/r_sci_uart.h|1119704027,rzn/fsp/inc/api/r_uart_api.h|3586794436,rzn/fsp/inc/api/r_transfer_api.h
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2 changes: 1 addition & 1 deletion projects/etherkit_basic_key_irq/buildinfo.ipcf
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Expand Up @@ -51,7 +51,7 @@
<group name="RA Smart Configurator">
<argVar>
<name>RASC_EXE_PATH</name>
<value>D:\manufacture_apps\Renesas\fsp\rzn_v2.0.0\eclipse\rasc.exe</value>
<value>C:\Renesas\rzn\sc_v2024-01.1_fsp_v2.0.0\eclipse\rasc.exe</value>
</argVar>
</group>
</customArgVars>
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2 changes: 1 addition & 1 deletion projects/etherkit_basic_key_irq/configuration.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -630,7 +630,7 @@
<node id="board.clock.pclkl.display" option="board.clock.pclkl.display.value"/>
<node id="board.clock.pclkadc.display" option="board.clock.pclkadc.display.value"/>
<node id="board.clock.pclkcan.freq" option="board.clock.pclkcan.freq.40m"/>
<node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.12m"/>
<node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.133m"/>
<node id="board.clock.xspi.clk1.freq" option="board.clock.xspi.clk1.freq.12m"/>
<node id="board.clock.tclk.freq" option="board.clock.tclk.freq.100m"/>
</raClockConfiguration>
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2 changes: 1 addition & 1 deletion projects/etherkit_basic_key_irq/rzn_cfg.txt
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Expand Up @@ -596,7 +596,7 @@ FSP Configuration
SPI2ASYNCCLK: 96MHz
SPI3ASYNCCLK: 96MHz
PCLKCAN 40MHz
XSPI_CLK0 12.5MHz
XSPI_CLK0 133.3MHz
XSPI_CLK1 12.5MHz

Pin Configurations
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2 changes: 1 addition & 1 deletion projects/etherkit_basic_key_irq/rzn_gen/bsp_clock_cfg.h
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Expand Up @@ -37,6 +37,6 @@
#define BSP_CFG_SPI2ASYNCCLK (BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI2ASYNCCLK: 96MHz */
#define BSP_CFG_SPI3ASYNCCLK (BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI3ASYNCCLK: 96MHz */
#define BSP_CFG_FSELCANFD (BSP_CLOCKS_CANFD_CLOCK_40_MHZ) /* PCLKCAN 40MHz */
#define BSP_CFG_FSELXSPI0_DIVSELXSPI0 (BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK0 12.5MHz */
#define BSP_CFG_FSELXSPI0_DIVSELXSPI0 (BSP_CLOCKS_XSPI0_CLOCK_DIV0_133_3_MHZ) /* XSPI_CLK0 133.3MHz */
#define BSP_CFG_FSELXSPI1_DIVSELXSPI1 (BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK1 12.5MHz */
#endif /* BSP_CLOCK_CFG_H_ */
2 changes: 1 addition & 1 deletion projects/etherkit_basic_rtc/.secure_xml
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Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@
<node id="board.clock.pclkl.display" option="board.clock.pclkl.display.value"/>
<node id="board.clock.pclkadc.display" option="board.clock.pclkadc.display.value"/>
<node id="board.clock.pclkcan.freq" option="board.clock.pclkcan.freq.40m"/>
<node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.12m"/>
<node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.133m"/>
<node id="board.clock.xspi.clk1.freq" option="board.clock.xspi.clk1.freq.12m"/>
<node id="board.clock.tclk.freq" option="board.clock.tclk.freq.100m"/>
</raClockConfiguration>
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4 changes: 2 additions & 2 deletions projects/etherkit_basic_rtc/.settings/standalone.prefs
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
#Wed Nov 27 16:37:16 CST 2024
#Thu Nov 28 17:28:34 CST 2024
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.0.0/all=907937621,script/fsp_xspi0_boot.icf|3822962514,rzn/board/rzn2l_rsk/board_leds.c|358444977,rzn/board/rzn2l_rsk/board_init.c|2067006575,rzn/board/rzn2l_rsk/board.h|736691883,rzn/board/rzn2l_rsk/board_ethernet_phy.h|1631979823,rzn/board/rzn2l_rsk/board_leds.h|1430483072,rzn/board/rzn2l_rsk/board_init.h
com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=
Expand All @@ -15,7 +15,7 @@ com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_rt
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp_xspi0_boot.icf
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.1.fsp.2.0.0/all=1441545198,rzn/arm/CMSIS_5/LICENSE.txt|4247764709,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h|1135074086,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h|510668081,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h|4245531541,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h|1887099957,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h|3334069041,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/all=
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=ClockGeneration
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.0.0/all=2921827146,rzn/fsp/src/r_sci_uart/r_sci_uart.c|4093801030,rzn/fsp/inc/instances/r_sci_uart.h|1119704027,rzn/fsp/inc/api/r_uart_api.h|3586794436,rzn/fsp/inc/api/r_transfer_api.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#\#\#2.0.0/all=3243637314,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
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2 changes: 1 addition & 1 deletion projects/etherkit_basic_rtc/buildinfo.ipcf
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Expand Up @@ -51,7 +51,7 @@
<group name="RA Smart Configurator">
<argVar>
<name>RASC_EXE_PATH</name>
<value>D:\manufacture_apps\Renesas\fsp\rzn_v2.0.0\eclipse\rasc.exe</value>
<value>C:\Renesas\rzn\sc_v2024-01.1_fsp_v2.0.0\eclipse\rasc.exe</value>
</argVar>
</group>
</customArgVars>
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2 changes: 1 addition & 1 deletion projects/etherkit_basic_rtc/configuration.xml
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Expand Up @@ -630,7 +630,7 @@
<node id="board.clock.pclkl.display" option="board.clock.pclkl.display.value"/>
<node id="board.clock.pclkadc.display" option="board.clock.pclkadc.display.value"/>
<node id="board.clock.pclkcan.freq" option="board.clock.pclkcan.freq.40m"/>
<node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.12m"/>
<node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.133m"/>
<node id="board.clock.xspi.clk1.freq" option="board.clock.xspi.clk1.freq.12m"/>
<node id="board.clock.tclk.freq" option="board.clock.tclk.freq.100m"/>
</raClockConfiguration>
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