Update cheri output

TUM-DSE · Feb 9, 2024 · 3a35d9c · 3a35d9c
1 parent ed918e3
commit 3a35d9c
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Showing 7 changed files with 91 additions and 29 deletions.
diff --git a/cranelift/codegen/meta/src/shared/instructions.rs b/cranelift/codegen/meta/src/shared/instructions.rs
@@ -679,7 +679,7 @@ pub(crate) fn define(
     let iAddr = &TypeVar::new(
         "iAddr",
         "An integer address type",
-        TypeSetBuilder::new().ints(32..64).refs(32..64).build(),
+        TypeSetBuilder::new().ints(32..64).refs(32..64).cap_ptrs(64..64).build(),
     );
 
     let Ref = &TypeVar::new(
@@ -706,6 +706,7 @@ pub(crate) fn define(
             .floats(Interval::All)
             .refs(Interval::All)
             .simd_lanes(Interval::All)
+            .cap_ptrs(Interval::All)
             .includes_scalars(true)
             .build(),
     );
@@ -768,7 +769,7 @@ pub(crate) fn define(
     let iExt8 = &TypeVar::new(
         "iExt8",
         "An integer type with more than 8 bits",
-        TypeSetBuilder::new().ints(16..64).build(),
+        TypeSetBuilder::new().ints(16..64).cap_ptrs(64..64).build(),
     );
 
     ig.push(

diff --git a/cranelift/codegen/src/isa/aarch64/inst.isle b/cranelift/codegen/src/isa/aarch64/inst.isle
@@ -133,6 +133,12 @@
         (mem AMode)
         (flags MemFlags))
 
+       ;; A capability load
+       (LoadC64
+        (rd WritableReg)
+        (mem AMode)
+        (flags MemFlags))
+
        ;; An 8-bit store.
        (Store8
         (rd Reg)
@@ -157,6 +163,12 @@
         (mem AMode)
         (flags MemFlags))
 
+       ;; A capability store
+       (StoreC64
+        (rd Reg)
+        (mem AMode)
+        (flags MemFlags))
+
        ;; A store of a pair of registers.
        (StoreP64
         (rt Reg)
@@ -3147,8 +3159,13 @@
       (let ((dst WritableReg (temp_writable_reg $I64))
             (_ Unit (emit (MInst.ULoad64 dst amode flags))))
         dst))
-(decl aarch64_loadC64 (CapAMode MemFlags) Reg)
+(decl aarch64_loadC64 (AMode MemFlags) Reg)
 (rule (aarch64_loadC64 amode flags)
+      (let ((dst WritableReg (temp_writable_reg $C64))
+            (_ Unit (emit (MInst.LoadC64 dst amode flags))))
+        dst))
+(decl aarch64_loadC64Alt (CapAMode MemFlags) Reg)
+(rule (aarch64_loadC64Alt amode flags)
       (let ((dst WritableReg (temp_writable_reg $C64))
             (_ Unit (emit (MInst.LoadC64Alt dst amode flags))))
         dst))
@@ -3188,8 +3205,11 @@
 (decl aarch64_store64 (AMode MemFlags Reg) SideEffectNoResult)
 (rule (aarch64_store64 amode flags val)
       (SideEffectNoResult.Inst (MInst.Store64 val amode flags)))
-(decl aarch64_store64C (CapAMode MemFlags Reg) SideEffectNoResult)
+(decl aarch64_store64C (AMode MemFlags Reg) SideEffectNoResult)
 (rule (aarch64_store64C amode flags val)
+      (SideEffectNoResult.Inst (MInst.StoreC64 val amode flags)))
+(decl aarch64_store64CAlt (CapAMode MemFlags Reg) SideEffectNoResult)
+(rule (aarch64_store64CAlt amode flags val)
       (SideEffectNoResult.Inst (MInst.StoreC64Alt val amode flags)))
 (decl aarch64_fpustore32 (AMode MemFlags Reg) SideEffectNoResult)
 (rule (aarch64_fpustore32 amode flags val)

diff --git a/cranelift/codegen/src/isa/aarch64/inst/args.rs b/cranelift/codegen/src/isa/aarch64/inst/args.rs
@@ -563,7 +563,7 @@ impl PrettyPrint for CapAMode {
     fn pretty_print(&self, _: u8, allocs: &mut AllocationConsumer<'_>) -> String {
         match self {
             &CapAMode::Unscaled { rn, simm9 } => {
-                let reg = pretty_print_reg(rn, allocs);
+                let reg = pretty_print_ireg(rn, OperandSize::Size64C, allocs);
                 if simm9.value != 0 {
                     let simm9 = simm9.pretty_print(8, allocs);
                     format!("[{}, {}]", reg, simm9)
@@ -572,7 +572,7 @@ impl PrettyPrint for CapAMode {
                 }
             }
             &CapAMode::UnsignedOffset { rn, uimm9 } => {
-                let reg = pretty_print_reg(rn, allocs);
+                let reg = pretty_print_ireg(rn, OperandSize::Size64C, allocs);
                 if uimm9.value != 0 {
                     let uimm9 = uimm9.pretty_print(8, allocs);
                     format!("[{}, {}]", reg, uimm9)
@@ -581,12 +581,12 @@ impl PrettyPrint for CapAMode {
                 }
             }
             &CapAMode::RegReg { rn, rm } => {
-                let r1 = pretty_print_reg(rn, allocs);
+                let r1 = pretty_print_ireg(rn, OperandSize::Size64C, allocs);
                 let r2 = pretty_print_reg(rm, allocs);
                 format!("[{}, {}]", r1, r2)
             }
             &CapAMode::RegScaled { rn, rm, ty } => {
-                let r1 = pretty_print_reg(rn, allocs);
+                let r1 = pretty_print_ireg(rn, OperandSize::Size64C, allocs);
                 let r2 = pretty_print_reg(rm, allocs);
                 let shift = shift_for_type(ty);
                 format!("[{}, {}, LSL #{}]", r1, r2, shift)
@@ -604,7 +604,7 @@ impl PrettyPrint for CapAMode {
                     }
                     _ => crate::isa::aarch64::inst::args::OperandSize::Size64,
                 };
-                let r1 = pretty_print_reg(rn, allocs);
+                let r1 = pretty_print_ireg(rn, OperandSize::Size64C, allocs);
                 let r2 = pretty_print_ireg(rm, size, allocs);
                 let op = extendop.pretty_print(0, allocs);
                 format!("[{}, {}, {} #{}]", r1, r2, op, shift)
@@ -616,7 +616,7 @@ impl PrettyPrint for CapAMode {
                     }
                     _ => crate::isa::aarch64::inst::args::OperandSize::Size64,
                 };
-                let r1 = pretty_print_reg(rn, allocs);
+                let r1 = pretty_print_ireg(rn, OperandSize::Size64C, allocs);
                 let r2 = pretty_print_ireg(rm, size, allocs);
                 let op = extendop.pretty_print(0, allocs);
                 format!("[{}, {}, {}]", r1, r2, op)

diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
@@ -1447,6 +1447,7 @@ impl MachInstEmit for Inst {
             | &Inst::ULoad64 {
                 rd, ref mem, flags, ..
             }
+            | &Inst::LoadC64 { rd, ref mem, flags }
             | &Inst::FpuLoad32 { rd, ref mem, flags }
             | &Inst::FpuLoad64 { rd, ref mem, flags }
             | &Inst::FpuLoad128 { rd, ref mem, flags } => {
@@ -1472,6 +1473,7 @@ impl MachInstEmit for Inst {
                     &Inst::ULoad32 { .. } => (0b1011100001, 32),
                     &Inst::SLoad32 { .. } => (0b1011100010, 32),
                     &Inst::ULoad64 { .. } => (0b1111100001, 64),
+                    &Inst::LoadC64 { .. } => (0b1010001001, 64),
                     &Inst::FpuLoad32 { .. } => (0b1011110001, 32),
                     &Inst::FpuLoad64 { .. } => (0b1111110001, 64),
                     &Inst::FpuLoad128 { .. } => (0b0011110011, 128),
@@ -1541,7 +1543,7 @@ impl MachInstEmit for Inst {
                                 sink.use_label_at_offset(
                                     sink.cur_offset(),
                                     *label,
-                                    LabelUse::Ldr19,
+                                    if matches!(self, &Inst::LoadC64 { .. }) { LabelUse::Ldr17 } else { LabelUse::Ldr19 },
                                 );
                                 0
                             }
@@ -1560,6 +1562,9 @@ impl MachInstEmit for Inst {
                             &Inst::ULoad64 { .. } => {
                                 sink.put4(enc_ldst_imm19(0b01011000, offset, rd));
                             }
+                            &Inst::LoadC64 { .. } => {
+                                sink.put4(enc_ldst_imm19(0b01011000, offset, rd));
+                            }
                             &Inst::FpuLoad64 { .. } => {
                                 sink.put4(enc_ldst_imm19(0b01011100, offset, rd));
                             }
@@ -1783,6 +1788,7 @@ impl MachInstEmit for Inst {
             | &Inst::Store16 { rd, ref mem, flags }
             | &Inst::Store32 { rd, ref mem, flags }
             | &Inst::Store64 { rd, ref mem, flags }
+            | &Inst::StoreC64 { rd, ref mem, flags }
             | &Inst::FpuStore32 { rd, ref mem, flags }
             | &Inst::FpuStore64 { rd, ref mem, flags }
             | &Inst::FpuStore128 { rd, ref mem, flags } => {
@@ -1799,6 +1805,7 @@ impl MachInstEmit for Inst {
                     &Inst::Store16 { .. } => (0b0111100000, 16),
                     &Inst::Store32 { .. } => (0b1011100000, 32),
                     &Inst::Store64 { .. } => (0b1111100000, 64),
+                    &Inst::StoreC64 { .. } => (0b1010001000, 64),
                     &Inst::FpuStore32 { .. } => (0b1011110000, 32),
                     &Inst::FpuStore64 { .. } => (0b1111110000, 64),
                     &Inst::FpuStore128 { .. } => (0b0011110010, 128),

diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
@@ -503,7 +503,8 @@ fn aarch64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
         | &Inst::SLoad16 { rd, ref mem, .. }
         | &Inst::ULoad32 { rd, ref mem, .. }
         | &Inst::SLoad32 { rd, ref mem, .. }
-        | &Inst::ULoad64 { rd, ref mem, .. } => {
+        | &Inst::ULoad64 { rd, ref mem, .. }
+        | &Inst::LoadC64 { rd, ref mem, .. } => {
             collector.reg_def(rd);
             memarg_operands(mem, collector);
         }
@@ -521,7 +522,8 @@ fn aarch64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
         &Inst::Store8 { rd, ref mem, .. }
         | &Inst::Store16 { rd, ref mem, .. }
         | &Inst::Store32 { rd, ref mem, .. }
-        | &Inst::Store64 { rd, ref mem, .. } => {
+        | &Inst::Store64 { rd, ref mem, .. }
+        | &Inst::StoreC64 { rd, ref mem, .. } => {
             collector.reg_use(rd);
             memarg_operands(mem, collector);
         }
@@ -1526,7 +1528,8 @@ impl Inst {
             | &Inst::SLoad16 { rd, ref mem, .. }
             | &Inst::ULoad32 { rd, ref mem, .. }
             | &Inst::SLoad32 { rd, ref mem, .. }
-            | &Inst::ULoad64 { rd, ref mem, .. } => {
+            | &Inst::ULoad64 { rd, ref mem, .. }
+            | &Inst::LoadC64 { rd, ref mem, .. } => {
                 let is_unscaled = match &mem {
                     &AMode::Unscaled { .. } => true,
                     _ => false,
@@ -1546,6 +1549,8 @@ impl Inst {
                     (&Inst::SLoad32 { .. }, true) => ("ldursw", OperandSize::Size64),
                     (&Inst::ULoad64 { .. }, false) => ("ldr", OperandSize::Size64),
                     (&Inst::ULoad64 { .. }, true) => ("ldur", OperandSize::Size64),
+                    (&Inst::LoadC64 { .. }, false) => ("ldr", OperandSize::Size64C),
+                    (&Inst::LoadC64 { .. }, true) => ("ldur", OperandSize::Size64C),
                     _ => unreachable!(),
                 };
 
@@ -1565,13 +1570,13 @@ impl Inst {
             | &Inst::ULoad64Alt { rd, ref mem, .. }
             | &Inst::LoadC64Alt { rd, ref mem, .. } => {
                 let (op, size) = match self {
-                    &Inst::ULoad8 { .. } => ("ldrb", OperandSize::Size32),
-                    &Inst::SLoad8 { .. } => ("ldrsb", OperandSize::Size64),
-                    &Inst::ULoad16 { .. } => ("ldrh", OperandSize::Size32),
-                    &Inst::SLoad16 { .. } => ("ldrsh", OperandSize::Size64),
-                    &Inst::ULoad32 { .. } => ("ldr", OperandSize::Size32),
-                    &Inst::SLoad32 { .. } => ("ldrsw", OperandSize::Size64),
-                    &Inst::ULoad64 { .. } => ("ldr", OperandSize::Size64),
+                    &Inst::ULoad8Alt { .. } => ("ldrb", OperandSize::Size32),
+                    &Inst::SLoad8Alt { .. } => ("ldrsb", OperandSize::Size64),
+                    &Inst::ULoad16Alt { .. } => ("ldrh", OperandSize::Size32),
+                    &Inst::SLoad16Alt { .. } => ("ldrsh", OperandSize::Size64),
+                    &Inst::ULoad32Alt { .. } => ("ldr", OperandSize::Size32),
+                    &Inst::SLoad32Alt { .. } => ("ldrsw", OperandSize::Size64),
+                    &Inst::ULoad64Alt { .. } => ("ldr", OperandSize::Size64),
                     &Inst::LoadC64Alt { .. } => ("ldr", OperandSize::Size64C),
                     _ => unreachable!(),
                 };
@@ -1585,7 +1590,8 @@ impl Inst {
             &Inst::Store8 { rd, ref mem, .. }
             | &Inst::Store16 { rd, ref mem, .. }
             | &Inst::Store32 { rd, ref mem, .. }
-            | &Inst::Store64 { rd, ref mem, .. } => {
+            | &Inst::Store64 { rd, ref mem, .. }
+            | &Inst::StoreC64 { rd, ref mem, .. } => {
                 let is_unscaled = match &mem {
                     &AMode::Unscaled { .. } => true,
                     _ => false,
@@ -1599,6 +1605,8 @@ impl Inst {
                     (&Inst::Store32 { .. }, true) => ("stur", OperandSize::Size32),
                     (&Inst::Store64 { .. }, false) => ("str", OperandSize::Size64),
                     (&Inst::Store64 { .. }, true) => ("stur", OperandSize::Size64),
+                    (&Inst::StoreC64 { .. }, false) => ("str", OperandSize::Size64C),
+                    (&Inst::StoreC64 { .. }, true) => ("stur", OperandSize::Size64C),
                     _ => unreachable!(),
                 };
 

diff --git a/cranelift/codegen/src/isa/aarch64/lower.isle b/cranelift/codegen/src/isa/aarch64/lower.isle
@@ -2301,8 +2301,11 @@
        (has_type $R64 (load flags address offset)))
       (aarch64_uload64 (amode $I64 address offset) flags))
 (rule (lower
-       (has_type $C64 (load flags address offset)))
-      (aarch64_loadC64 (cap_amode $I64 address offset) flags))
+       (has_type $C64 (load flags address @ (value_type $I64) offset)))
+      (aarch64_loadC64 (amode $C64 address offset) flags))
+(rule (lower
+       (has_type $C64 (load flags address @ (value_type $C64) offset)))
+      (aarch64_loadC64Alt (cap_amode $C64 address offset) flags))
 (rule (lower
        (has_type $F32 (load flags address offset)))
       (aarch64_fpuload32 (amode $F32 address offset) flags))
@@ -2408,9 +2411,13 @@
       (side_effect
        (aarch64_store64 (amode $I64 address offset) flags value)))
 (rule (lower
-       (store flags value @ (value_type $C64) address offset))
+       (store flags value @ (value_type $C64) address @ (value_type $I64) offset))
+      (side_effect
+       (aarch64_store64C (amode $I64 address offset) flags value)))
+(rule (lower
+       (store flags value @ (value_type $C64) address @ (value_type $C64) offset))
       (side_effect
-       (aarch64_store64C (cap_amode $I64 address offset) flags value)))
+       (aarch64_store64CAlt (cap_amode $I64 address offset) flags value)))
 
 (rule (lower
        (istore8 flags value address offset))

diff --git a/cranelift/filetests/filetests/isa/aarch64/capabilities.clif b/cranelift/filetests/filetests/isa/aarch64/capabilities.clif
@@ -2,7 +2,7 @@ test compile precise-output
 set unwind_info=false
 target aarch64
 
-function %f5(i64) {
+function %f1(i64) {
 block0(v0: i64):
   v1 = load.c64 v0
   store.c64 v1, v0
@@ -17,7 +17,26 @@ block0(v0: i64):
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   prfb pldl2keep, p0, [x0, #-0x20, mul vl]
-;   prfb pldl2keep, p0, [x0]
+;   .byte 0x02, 0x00, 0x40, 0xa3
+;   .byte 0x02, 0x00, 0x00, 0xa3
+;   ret
+
+function %f2(c64) {
+block0(v0: c64):
+  v1 = load.c64 v0
+  store.c64 v1, v0
+  return
+}
+
+; VCode:
+; block0:
+;   ldr c2, [c0]
+;   str c2, [c0]
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x02, 0x00, 0x60, 0x82
+;   .byte 0x02, 0x00, 0x40, 0x82
 ;   ret