Fix encoding

TUM-DSE · Feb 26, 2024 · c3d07b1 · c3d07b1
1 parent ea54c5e
commit c3d07b1
Show file tree

Hide file tree

Showing 3 changed files with 69 additions and 31 deletions.
diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
@@ -1650,19 +1650,16 @@ impl MachInstEmit for Inst {
                     &Inst::SLoad8Alt { .. } => (0b10000010100, 0b01, 8),
                     &Inst::ULoad16Alt { .. } => (0b10000010110, 0b11, 16),
                     &Inst::SLoad16Alt { .. } => (0b10000010100, 0b10, 16),
-                    &Inst::ULoad32Alt { .. } => (0b10000000111, 0b00, 32),
+                    &Inst::ULoad32Alt { .. } => (0b10000010111, 0b00, 32),
+                    &Inst::ULoad64Alt { .. } => (0b10000010111, 0b01, 64),
+                    &Inst::LoadC64Alt { .. } => (0b11000010111, 0b11, 64),
                     &Inst::SLoad32Alt { .. } => {
-                        assert!(!matches!(
+                        assert!(matches!(
                             &mem,
-                            &CapAMode::RegReg { .. }
-                                | &CapAMode::RegScaled { .. }
-                                | &CapAMode::RegScaledExtended { .. }
-                                | &CapAMode::RegExtended { .. }
+                            &CapAMode::Unscaled { .. }
                         ));
                         (0, 0, 32)
                     }
-                    &Inst::ULoad64Alt { .. } => (0b10000000111, 0b01, 64),
-                    &Inst::LoadC64Alt { .. } => (0b11000010111, 0b11, 64),
                     &Inst::FpuLoad32Alt { .. } => todo!(),
                     &Inst::FpuLoad64Alt { .. } => todo!(),
                     &Inst::FpuLoad128Alt { .. } => todo!(),
@@ -1775,25 +1772,25 @@ impl MachInstEmit for Inst {
                             &Inst::LoadC64Alt { .. } => {
                                 sink.put4(enc_ldst_imm17(0b1000001000, offset, rd));
                             }
-                            // For the remaining ones, just use the non-alternate version.
-                            &Inst::ULoad32Alt { .. } => {
-                                sink.put4(enc_ldst_imm19(0b00011000, offset, rd));
-                            }
-                            &Inst::SLoad32Alt { .. } => {
-                                sink.put4(enc_ldst_imm19(0b10011000, offset, rd));
-                            }
-                            &Inst::FpuLoad32Alt { .. } => {
-                                sink.put4(enc_ldst_imm19(0b00011100, offset, rd));
-                            }
-                            &Inst::ULoad64Alt { .. } => {
-                                sink.put4(enc_ldst_imm19(0b01011000, offset, rd));
-                            }
-                            &Inst::FpuLoad64Alt { .. } => {
-                                sink.put4(enc_ldst_imm19(0b01011100, offset, rd));
-                            }
-                            &Inst::FpuLoad128Alt { .. } => {
-                                sink.put4(enc_ldst_imm19(0b10011100, offset, rd));
-                            }
+                            // // For the remaining ones, just use the non-alternate version.
+                            // &Inst::ULoad32Alt { .. } => {
+                            //     sink.put4(enc_ldst_imm19(0b00011000, offset, rd));
+                            // }
+                            // &Inst::SLoad32Alt { .. } => {
+                            //     sink.put4(enc_ldst_imm19(0b10011000, offset, rd));
+                            // }
+                            // &Inst::FpuLoad32Alt { .. } => {
+                            //     sink.put4(enc_ldst_imm19(0b00011100, offset, rd));
+                            // }
+                            // &Inst::ULoad64Alt { .. } => {
+                            //     sink.put4(enc_ldst_imm19(0b01011000, offset, rd));
+                            // }
+                            // &Inst::FpuLoad64Alt { .. } => {
+                            //     sink.put4(enc_ldst_imm19(0b01011100, offset, rd));
+                            // }
+                            // &Inst::FpuLoad128Alt { .. } => {
+                            //     sink.put4(enc_ldst_imm19(0b10011100, offset, rd));
+                            // }
                             _ => panic!("Unspported size for LDR from constant pool!"),
                         }
                     }

diff --git a/cranelift/filetests/filetests/isa/aarch64/capabilities.clif b/cranelift/filetests/filetests/isa/aarch64/capabilities.clif
@@ -264,3 +264,43 @@ block0(v0: i64):
 ;   .byte 0x80, 0x00, 0xc5, 0xc2
 ;   ret
 
+function %mem_grow(i64, i64, i32) -> i32 fast {
+block0(v0: i64, v1: i64, v2: i32):
+  v6 -> v0
+  v17 -> v0
+  v18 -> v0
+  v7 = load.i64 notrap aligned readonly v0+56
+  v8 = load.i64 notrap aligned readonly v7
+  v19 = iconst.i64 1
+  v5 = iconst.i32 0
+;;  v10 = call_indirect sig1, v8(v0, v19, v5)  ; v19 = 1, v5 = 0
+  v14 = load.c64 notrap aligned checked v0+80
+  v12 = uextend.i64 v2
+  v15 = cadd v14, v12
+  v16 = load.i32 little heap v15
+  v3 -> v16
+  jump block1
+
+block1:
+  return v16
+}
+
+; VCode:
+; block0:
+;   ldr x7, [x0, #56]
+;   ldr x7, [x7]
+;   ldr c7, [x0, #80]
+;   ldr w0, [c7, w2, UXTW]
+;   b label1
+; block1:
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   ldr x7, [x0, #0x38]
+;   ldr x7, [x7]
+;   .byte 0x07, 0x14, 0x40, 0xc2
+;   .byte 0xe0, 0x40, 0xe2, 0x82
+; block1: ; offset 0x10
+;   ret
+
diff --git a/tests/cheri/load_store_simple.wat b/tests/cheri/load_store_simple.wat
@@ -1,10 +1,11 @@
 (module
-  (memory i32 2)
+  (memory i32 1)
 
-  (func (export "do_store_0") (param i64)
-    i32.const 0
+  (func (export "do_load0") (param i32) (result i32)
+    (memory.grow (i32.const 1))
+    drop
     local.get 0
-    i64.store offset=0)
+    i32.load offset=0)
 
   (func (export "do_store") (param i32 i32)
     local.get 0