add support for cadd

cranelift/codegen/meta/src/shared/instructions.rs

@@ -630,6 +630,7 @@ pub(crate) fn define(
 
     // Operand kind shorthands.
     let i8: &TypeVar = &ValueType::from(LaneType::from(types::Int::I8)).into();
+    let i64: &TypeVar = &ValueType::from(LaneType::from(types::Int::I64)).into();
     let f32_: &TypeVar = &ValueType::from(LaneType::from(types::Float::F32)).into();
     let f64_: &TypeVar = &ValueType::from(LaneType::from(types::Float::F64)).into();
 
@@ -3827,7 +3828,7 @@ pub(crate) fn define(
         )
         .operands_in(vec![
             Operand::new("x", CapPtr).with_doc("The first capability"),
-            Operand::new("y", Int).with_doc("The value being added"),
+            Operand::new("y", i64).with_doc("The value being added"),
         ])
         .operands_out(vec![
             Operand::new("a", CapPtr).with_doc("The result of the addition")

cranelift/codegen/src/isa/aarch64/inst.isle

@@ -2209,6 +2209,12 @@
             (_ Unit (emit (MInst.CapOpRRR op dst src1 src2 (ExtendOp.UXTX)))))
         dst))
 
+(decl cap_rrr_extend (CapOp Type Reg ExtendedValue) Reg)
+(rule (cap_rrr_extend op ty src1 src2)
+      (let ((dst WritableReg (temp_writable_reg $C64))
+            (_ Unit (emit (MInst.CapOpRRR op dst src1 (put_extended_in_reg src2) (get_extended_op src2)))))
+        dst))
+
 ;; Helper for emitting `MInst.VecRRR` instructions.
 (decl vec_rrr (VecALUOp Reg Reg VectorSize) Reg)
 (rule (vec_rrr op src1 src2 size)
@@ -2753,6 +2759,7 @@
 
 (decl add_extend (Type Reg ExtendedValue) Reg)
 (rule (add_extend ty x y) (alu_rr_extend_reg (ALUOp.Add) ty x y))
+(rule 1 (add_extend $C64 x y) (cap_rrr_extend (CapOp.Add) $C64 x y))
 
 (decl add_extend_op (Type Reg Reg ExtendOp) Reg)
 (rule (add_extend_op ty x y extend) (alu_rrr_extend (ALUOp.Add) ty x y extend))
@@ -2775,6 +2782,7 @@
 
 (decl sub_extend (Type Reg ExtendedValue) Reg)
 (rule (sub_extend ty x y) (alu_rr_extend_reg (ALUOp.Sub) ty x y))
+(rule 1 (sub_extend $C64 x y) (cap_rrr_extend (CapOp.Sub) $C64 x y))
 
 (decl sub_shift (Type Reg Reg ShiftOpAndAmt) Reg)
 (rule (sub_shift ty x y z) (alu_rrr_shift (ALUOp.Sub) ty x y z))

cranelift/codegen/src/isa/aarch64/inst/mod.rs

@@ -1505,7 +1505,17 @@ impl Inst {
                 let op = cap_op_name(cap_op);
                 let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64C, allocs);
                 let rn = pretty_print_ireg(rn, OperandSize::Size64C, allocs);
-                let rm = pretty_print_ireg(rm, OperandSize::Size64C, allocs);
+                let rm_size = match extendop {
+                    ExtendOp::UXTB |
+                    ExtendOp::SXTB |
+                    ExtendOp::UXTH |
+                    ExtendOp::SXTH |
+                    ExtendOp::UXTW |
+                    ExtendOp::SXTW => OperandSize::Size32,
+                    ExtendOp::UXTX |
+                    ExtendOp::SXTX => OperandSize::Size64,
+                };
+                let rm = pretty_print_ireg(rm, rm_size, allocs);
                 let extendop = extendop.pretty_print(0, allocs);
                 format!("{} {}, {}, {}, {}", op, rd, rn, rm, extendop)
             }

cranelift/codegen/src/isa/aarch64/lower.isle

@@ -45,6 +45,13 @@
 (rule -1 (lower (cadd x y))
       (add $C64 x y))
 
+(rule 0 (lower (cadd x (extended_value_from_value y)))
+      (add_extend $C64 x y))
+
+;; Special cases for when one operand is an immediate that fits in 12 bits.
+(rule 4 (lower (cadd x (imm12_from_value y)))
+      (add_imm $C64 x y))
+
 ;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; `i64` and smaller

cranelift/filetests/filetests/isa/aarch64/capabilities.clif

@@ -88,11 +88,46 @@ block0(v0: c64, v1: i64):
 
 ; VCode:
 ; block0:
-;   add c0, c0, c1, UXTX
+;   add c0, c0, x1, UXTX
 ;   ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   .byte 0x00, 0x60, 0xa1, 0xc2
 ;   ret
 
+function %f5(c64, i32) -> c64 {
+block0(v0: c64, v1: i32):
+  v2 = uextend.i64 v1
+  v3 = cadd v0, v2
+  return v3
+}
+
+; VCode:
+; block0:
+;   add c0, c0, w1, UXTW
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x00, 0x40, 0xa1, 0xc2
+;   ret
+
+
+function %f6(c64) -> c64 {
+block0(v0: c64):
+  v1 = iconst.i64 1
+  v2 = cadd v0, v1
+  return v2
+}
+
+; VCode:
+; block0:
+;   add c0, c0, #1
+;   ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+;   .byte 0x00, 0x04, 0x00, 0x02
+;   ret
+