Tanmaymundra / vhdl Public

This repository contains example of logic such as comparator, encoder, etc in vhdl. Feel Free to add other examples in this repository

tanmaymundra.github.io/vhdl

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Name		Name	Last commit message	Last commit date
Latest commit History 76 Commits
1bit_comp.vhd		1bit_comp.vhd
2bit_comp.vhd		2bit_comp.vhd
4:1 MUX.vhd		4:1 MUX.vhd
4:2 Encoder.vhd		4:2 Encoder.vhd
8:3 Encoder.vhd		8:3 Encoder.vhd
Asynchronous 3bit up(JK FF).vhd		Asynchronous 3bit up(JK FF).vhd
BCD to EX3.vhd		BCD to EX3.vhd
BCD_Gray.vhd		BCD_Gray.vhd
D FF.vhd		D FF.vhd
Gray_BCD.vhd		Gray_BCD.vhd
JK FF.vhd		JK FF.vhd
Q5.a -2017-18 Dsd		Q5.a -2017-18 Dsd
README.md		README.md
Ring Counter - D FF.vhd		Ring Counter - D FF.vhd
SR FF.vhd		SR FF.vhd
Shift Registers -PIPO.vhd		Shift Registers -PIPO.vhd
Shift Registers -PISO.vhd		Shift Registers -PISO.vhd
Shift Registers -SIPO.vhd		Shift Registers -SIPO.vhd
Shift Registers -SISO.vhd		Shift Registers -SISO.vhd
Synchronous Counter (4 Bit).vhd		Synchronous Counter (4 Bit).vhd
T FF.vhd		T FF.vhd
_config.yml		_config.yml
seq_det.vhd		seq_det.vhd