v0.6.0

Separated source and accumulation registers
More flexible register shape
More Element-wise instruction

Full Changelog**: v0.4.0...v0.6.0**

matrix specification for race

Spec under branch xuantie_race

1. 16 Two Dimensional Scalable Matrix Register
2. Three Matrix Multiplication Mode Supported
3. 64-bit Encoding

RISC-V Matrix Multiplication Extension Specification v0.4.0

update logs from v0.3
spec

1. remove matrix-scalar instructions
2. remove matrix-vector instructions which vector operand is indexed by scalar register
3. change misa definition
4. add float pointwise instructions
5. add some integer pointwise instructions
6. add integer float conversion instructions
7. add matrix memory model
8. update pointwise instructions' opcodes
9. fix other minor bugs

demos
add configure examples for cpf

toolchain and simulation tools are still based on v0.3(not updated)

RISC-V Matrix Multiplication Extension Specification v0.3.0

RISC-V Matrix Multiplication Extension Specification v0.3.0
Update log compared to v0.1.0：

• Add widen floating-point matrix multiplication instructions for mixed precision

• Add move instruction between scalar registers and matrix registers for debug purpose

• Change mrelease to initial ms status/add mzero for security issues

• Remove streaming memory access instruction, Compatible with zhintntl extensions instead of customizing hint operations in extensions

• Support new data types int4/bf16

• Add RLEN, modify MLEN definition for a clearer programming model

• Reorganize the matrix CSR to be more accurate and meet the RISC-V standards

• Modify arithmetic instructions opcode, more consistent with RISC-V coding habits

• New intrinsic style with function overloading

RISC-V Matrix Multiplication Extension Specification v0.1.0

RISC-V Matrix Multiplication Extension Specification v0.1.0