common: Use NPNR_ASSERT_FALSE for unreachable case

YosysHQ · Sep 24, 2024 · 0af42f1 · 0af42f1
1 parent 93e233d
commit 0af42f1
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Showing 2 changed files with 5 additions and 6 deletions.
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
@@ -30,7 +30,6 @@
 #include "archdefs.h"
 #include "hashlib.h"
 #include "indexed_store.h"
-#include "log.h"
 #include "nextpnr_base_types.h"
 #include "nextpnr_namespaces.h"
 #include "property.h"
@@ -201,7 +200,7 @@ enum PortType
     case PORT_INOUT:
         return "PORT_INOUT";
     default:
-        log_error("Impossible PortType");
+        NPNR_ASSERT_FALSE("Impossible PortType");
     }
 }
 
@@ -250,7 +249,7 @@ enum TimingPortClass
     case TMG_IGNORE:
         return "TMG_IGNORE";
     default:
-        log_error("Impossible TimingPortClass");
+        NPNR_ASSERT_FALSE("Impossible TimingPortClass");
     }
 }
 
@@ -268,7 +267,7 @@ enum ClockEdge
     case FALLING_EDGE:
         return "FALLING_EDGE";
     default:
-        log_error("Impossible ClockEdge");
+        NPNR_ASSERT_FALSE("Impossible ClockEdge");
     }
 }
 
@@ -438,7 +437,7 @@ struct CriticalPath
             case Type::HOLD:
                 return "hold";
             default:
-                log_error("Impossible Segment::Type");
+                NPNR_ASSERT_FALSE("Impossible Segment::Type");
             }
         }
 

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
@@ -1318,7 +1318,7 @@ const std::string TimingAnalyser::arcType_to_str(CellArc::ArcType typ)
     case TimingAnalyser::CellArc::ENDPOINT:
         return "ENDPOINT";
     default:
-        log_error("Impossible CellArc::ArcType\n");
+        NPNR_ASSERT_FALSE("Impossible CellArc::ArcType\n");
     }
 }