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自作CPU(RISC-V: RV32I) / 筑波大学 COJT HWコース

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Name		Name	Last commit message	Last commit date
Latest commit History 88 Commits
SIM		SIM
cpu_core_1.0		cpu_core_1.0
cpu_core_controller_1.0		cpu_core_controller_1.0
cpu_proj.sdk		cpu_proj.sdk
.gitignore		.gitignore
README.md		README.md
cpu_proj.tcl		cpu_proj.tcl
cpu_proj.xdc		cpu_proj.xdc
cpu_proj.xpr		cpu_proj.xpr

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COJTHW-CPUProj

概要

自作CPU (ISA : RISC-V/rv32i)
自作CPU上で動く自作OS COJTHW-SiCOS

IP

cpu_core_1.0

CPU本体

cpu_core_controller_1.0

PSからCPUを制御するための回路

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自作CPU(RISC-V: RV32I) / 筑波大学 COJT HWコース

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