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VHDL Generation #177

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697aedc
SQUASHED:
ahadnagy Apr 15, 2020
a76531b
Branch off from new_grammar, merge abs-tudelft/master (manual conflic…
matthijsr Jul 28, 2021
fcb11b4
Dependencies, dependabot
matthijsr Jul 28, 2021
c88ccb0
Some initial concepts.
matthijsr Jul 28, 2021
f7d6d81
Reorganize module a bit, try out VHDL package generation
matthijsr Jul 29, 2021
66be8f4
Stub can be source, sink or passthrough.
matthijsr Jul 29, 2021
c02db14
Test error as well
matthijsr Jul 29, 2021
a75e401
Refactoring, move ImplementationBackend to its own module.
matthijsr Jul 30, 2021
58622b9
Store interfaces in BTreeMap to ensure they are ordered. (Tests may f…
matthijsr Jul 30, 2021
f098e96
Try out some vhdl generation. Change record declaration syntax.
matthijsr Aug 4, 2021
4b6c4ad
Declare usings when declaring package
matthijsr Aug 4, 2021
ba5dde6
Unions and higher throughput doesn't seem to be converted correctly, …
matthijsr Aug 5, 2021
83b4cf5
Trying some VHDL constructs to make unions easier to work with. (This…
matthijsr Aug 5, 2021
7813ecc
This looks to be the only real solution
matthijsr Aug 5, 2021
b3be13e
Just let stubs handle anything that gets thrown at them.
matthijsr Aug 6, 2021
10caca8
Need to consider how to set up arrays, think I might just pass identi…
matthijsr Aug 6, 2021
6d845ff
Like so, probably.
matthijsr Aug 6, 2021
7d5817b
Generate array declarations. This broke Chisel, unfortunately, but th…
matthijsr Aug 6, 2021
fa545c9
Overlooked a match
matthijsr Aug 6, 2021
f93c7de
Refactor ports declaration, re-use for entity declaration.
matthijsr Aug 6, 2021
d62b9a9
Some preliminary notes on architecture generation
matthijsr Aug 6, 2021
e723abc
Some more preliminary notes on architecture generation
matthijsr Aug 6, 2021
c80b37e
Refactoring usings, stdlib common organization
matthijsr Aug 8, 2021
317c854
Further refactoring, usings for Architecture
matthijsr Aug 8, 2021
2bd083e
Architecture declaration
matthijsr Aug 8, 2021
2752b44
enum might make sense for arch declarations
matthijsr Aug 8, 2021
f9dd733
Slightly more variety in generating package
matthijsr Aug 11, 2021
03e49a7
Make arrays "... to ..." instead of "... downto ..."
matthijsr Aug 11, 2021
a0a6e60
Revert array changes, make note for myself.
matthijsr Aug 11, 2021
9106fcb
fmt
matthijsr Aug 11, 2021
190d51c
New basis for constructs
matthijsr Aug 11, 2021
d13a6f9
Consider what a wrapper should be generating. This is correct VHDL, a…
matthijsr Aug 11, 2021
83bb42e
Commit this, then start reverting it. Make unions regular records.
matthijsr Aug 12, 2021
7a86ea9
Union contains Record struct.
matthijsr Aug 12, 2021
965dd3d
Cleanup, actualy use Union
matthijsr Aug 12, 2021
d4d6fbf
Optional documentation on Fields. Use to list variants on tag in reco…
matthijsr Aug 12, 2021
53651d2
Signal/value assignment constructs, WIP
matthijsr Aug 13, 2021
da5bc75
Logic for assigning bit vectors
matthijsr Aug 13, 2021
e260cd0
Objects and aliases
matthijsr Aug 13, 2021
8408c71
Lots of yak-shaving, need to rethink this
matthijsr Aug 15, 2021
d29f53f
This makes a bit more sense already
matthijsr Aug 15, 2021
97c4c86
Alias, field selection + verification
matthijsr Aug 15, 2021
3b5a280
wip
matthijsr Aug 18, 2021
1729526
Direct assignment of bits and bitvecs displays correctly
matthijsr Aug 18, 2021
0f302a4
More edge-cases
matthijsr Aug 18, 2021
f5f2ced
Printing record assignment
matthijsr Aug 19, 2021
7cb78d1
Lots of refactoring, but worth it.
matthijsr Aug 19, 2021
6a98f80
Assign is working, and can_assign is partially finished.
matthijsr Aug 19, 2021
1ff932d
Full assigns not ready yet.
matthijsr Aug 19, 2021
9e5d9e5
Use impl Into more, add documentation to assignments
matthijsr Aug 20, 2021
1ba6a2c
Record assignment and check
matthijsr Aug 20, 2021
5b186c4
All checks done, give up on mode checks for now.
matthijsr Aug 20, 2021
a8effad
Declarations galore
matthijsr Aug 22, 2021
281468c
Port mapping declarations
matthijsr Aug 25, 2021
19a1b40
Convert records object assignments to full record assignments to hand…
matthijsr Aug 25, 2021
40403c3
Enable unwrapping array assignments as well, and combine both methods.
matthijsr Aug 25, 2021
3fd9186
Work on the wrapper, need to support flattening/unflattening first.
matthijsr Aug 26, 2021
d377dad
Clean up unused imports to reduce warnings
matthijsr Aug 27, 2021
38c5565
Flattening arrays works
matthijsr Aug 27, 2021
01b59cb
Concat LSB-first. Union handling
matthijsr Aug 27, 2021
3c7c454
Unions kinda work, need to be rewritten not to assign multiple to the…
matthijsr Aug 27, 2021
9f0811f
Split to_complex solution off for unions, add note indicating that th…
matthijsr Aug 27, 2021
10cc21f
Flattening is as good as it's gonna get for the time being. Still nee…
matthijsr Aug 27, 2021
00d8320
At least use what I've got to show off some more comprehensive archit…
matthijsr Aug 28, 2021
9cbb44c
Remove unnecessary port map.
matthijsr Aug 29, 2021
bbc5108
Fix tests that broke due to union
matthijsr Aug 29, 2021
05b970f
Fancy wrapper works, but port mapping from signals is complicated due…
matthijsr Aug 29, 2021
8a149dc
Make sure arrays split correctly, function to create separate object …
matthijsr Aug 29, 2021
336745a
VHDL generation now generates wrappers for fancy variants of components
matthijsr Aug 29, 2021
21046f6
Rebased again, just ignored Cargo.lock, then deleted it and ran cargo…
matthijsr Aug 31, 2021
baf083c
Once again, rebase and fix up cargo.lock
matthijsr Aug 31, 2021
6887ce5
Remove most of Akos's generator code. Make sure cargo test passes.
matthijsr Sep 23, 2021
b04b1c0
Cargo fix. Remove unused imports. Allow two instances of dead code.
matthijsr Sep 23, 2021
13e5291
cargo fmt
matthijsr Sep 23, 2021
f68d6ee
Revert logo change
matthijsr Sep 23, 2021
7a0a91b
Merge remote-tracking branch 'abs/master' into stdlib/develop
matthijsr Sep 23, 2021
e82dcb3
Remove unused dependencies
matthijsr Sep 23, 2021
98fc91c
Remove some playground tests, replace prints with asserts where relev…
matthijsr Sep 23, 2021
25582f1
Test file generation with tempdir
matthijsr Sep 23, 2021
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2 changes: 1 addition & 1 deletion .github/dependabot.yml
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ updates:
time: "04:00"
open-pull-requests-limit: 10
assignees:
- mbrobbel
- matthijsr
allow:
- dependency-type: direct
- dependency-type: indirect
Expand Down
7 changes: 6 additions & 1 deletion .gitignore
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
# Clion
# IDEs
.idea
.vscode

# Book
book/book
Expand All @@ -8,3 +9,7 @@ book/book
/target
**/*.rs.bk
tarpaulin-report.html

# Output
/output
*.cf
3 changes: 2 additions & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,10 @@ required-features = ["cli"]

[features]
cli = ["structopt", "parser"]
default = ["generator", "parser"]
default = ["generator", "parser", "stdlib"]
generator = []
parser = ["nom"]
stdlib = ["generator"]

[dependencies]
log = "0.4"
Expand Down
9 changes: 5 additions & 4 deletions src/bin/tydi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2,17 +2,18 @@
//!
//! The Command-Line Interface binary is enabled by the `cli` feature flag.

use log::{debug, info, LevelFilter};
use std::convert::TryInto;
use std::path::{Path, PathBuf};

use log::{debug, info, LevelFilter};
use structopt::StructOpt;

use tydi::design::{Library, Project};
use tydi::generator::vhdl::{VHDLBackEnd, VHDLConfig};
use tydi::generator::GenerateProject;
use tydi::UniquelyNamedBuilder;
use tydi::{Logger, Result};

use structopt::StructOpt;
use tydi::design::{Library, Project};

static LOGGER: Logger = Logger;

/// Back-end options.
Expand Down
19 changes: 19 additions & 0 deletions src/design/implementation/composer/impl_backend/mod.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,19 @@
use crate::design::StreamletHandle;
use crate::error::Result;
use crate::Name;
use core::fmt::{Debug, Formatter};

///Trait for general implementation backends
pub trait ImplementationBackend {
fn name(&self) -> Name;
fn streamlet_handle(&self) -> StreamletHandle;
fn connect_action(&self) -> Result<()> {
unimplemented!()
}
}

impl Debug for dyn ImplementationBackend {
fn fmt(&self, _f: &mut Formatter<'_>) -> std::fmt::Result {
unimplemented!()
}
}
110 changes: 110 additions & 0 deletions src/design/implementation/composer/mod.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,110 @@
use std::cell::{Ref, RefMut};
use std::rc::Rc;

use crate::design::implementation::Implementation;
use crate::design::{ComponentKey, IFKey, Interface, Mode, Streamlet};
use crate::Result;

pub mod impl_backend;
pub mod patterns;

/// Traits for components in the implementation graph
pub trait GenHDL {
fn gen_hdl(&self) -> Result<String>;
}

pub trait GenericComponent {
fn key(&self) -> ComponentKey {
self.streamlet().key().clone()
}
fn interfaces<'a>(&'a self) -> Box<(dyn Iterator<Item = Ref<Interface>> + 'a)> {
self.streamlet().interfaces()
}
fn interfaces_mut<'a>(&'a self) -> Box<(dyn Iterator<Item = RefMut<Interface>> + 'a)> {
unimplemented!()
}
fn streamlet(&self) -> &Streamlet;
fn inputs<'a>(&'a self) -> Box<(dyn Iterator<Item = Ref<Interface>> + 'a)> {
Box::new(self.interfaces().filter(|iface| iface.mode() == Mode::In))
}
fn outputs<'a>(&'a self) -> Box<(dyn Iterator<Item = Ref<Interface>> + 'a)> {
Box::new(self.interfaces().filter(|iface| iface.mode() == Mode::Out))
}
fn get_interface(&self, key: IFKey) -> Result<Ref<Interface>> {
self.streamlet().get_interface(key)
}
fn get_interface_mut(&self, key: IFKey) -> Result<RefMut<Interface>> {
self.streamlet().get_interface_mut(key)
}
fn get_implementation(&self) -> Option<Rc<Implementation>> {
self.streamlet().get_implementation()
}
fn connect_action(&self) -> Result<()> {
Ok(())
}
}

#[cfg(test)]
mod tests {
use crate::design::*;
use std::convert::TryFrom;

use crate::parser::nom::interface;
use crate::{Name, Result, UniqueKeyBuilder};

pub(crate) fn composition_test_proj() -> Result<Project> {
let key1 = LibKey::try_new("primitives").unwrap();
let key2 = LibKey::try_new("compositions").unwrap();
let mut lib = Library::new(key1.clone());

let mut lib_comp = Library::new(key2.clone());

let _top = lib_comp
.add_streamlet(
Streamlet::from_builder(
StreamletKey::try_from("Top_level").unwrap(),
UniqueKeyBuilder::new().with_items(vec![
interface("in: in Stream<Bits<32>, d=1>").unwrap().1,
interface("in2: in Stream<Bits<1>, d=0>").unwrap().1,
interface("out: out Stream<Bits<32>, d=0>").unwrap().1,
]),
None,
)
.unwrap(),
)
.unwrap();

let _map = lib
.add_streamlet(
Streamlet::from_builder(
StreamletKey::try_from("Magic").unwrap(),
UniqueKeyBuilder::new().with_items(vec![
interface("in: in Stream<Bits<32>, d=1>").unwrap().1,
interface("out: out Stream<Bits<32>, d=1>").unwrap().1,
]),
None,
)
.unwrap(),
)
.unwrap();

let _test_op = lib
.add_streamlet(
Streamlet::from_builder(
StreamletKey::try_from("test_op").unwrap(),
UniqueKeyBuilder::new().with_items(vec![
interface("in: in Stream<Bits<32>, d=0>").unwrap().1,
interface("out: out Stream<Bits<32>, d=0>").unwrap().1,
]),
None,
)
.unwrap(),
)
.unwrap();

let mut prj = Project::new(Name::try_new("TestProj").unwrap());
prj.add_lib(lib)?;
prj.add_lib(lib_comp)?;
Ok(prj)
}
}
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