This repository is an excuse to learn abount Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to make good use of the tools I enjoy the most for digital design. These include nmigen, cocotb, yosys, icarus verilog, gtkwave.
The main goal is to have an easy python2fpga port by generating a Verilog file from a trained nn designed with some Python lib like Keras.
The status of this project is "very" WIP!
To do (HDL):
- MACC: HDL + testbench (should be reimplemented to infer arch dependent dsp slices)
- Pipelined tree adder: HDL + testbench
- Dot product: HDL + testbench
- Dot product array (farm): HDL + testbench
- Row Fifo: HDL + testbench
- MatrixFeeder: HDL + testbench
- MatrixStream interface
- Implement MatrixStream interface in existing cores
- Convolution: HDL + testbench
- Resizer (Padder & Cropper): HDL + testbench
- Convolution Layer
- StreamWrapper for logic with clken
- Pooling: HDL + testbench
- ReLU
- Ciruclar ROM: HDL + testbench
- Stream MACC: HDL + testbench
- Sigmoid / Softmax
- MLP node
- MLP layer
- CNN (Customizable integration of the cores above)
- UART interface to be able to run some tests in hw with a low-cost fpga (only as a proof of concept)
- PC: Python Uart Tx/Rx
- python2fpga (integration with keras?)
To do (enhacements):
- Paralell convolution by splitting input image
To do (tools):
- Dockerfile
- CI
- Python package
- Example of verilog generation
To do (others):
- Organize files, interfaces, etc. (this one will remain "undone" until a more stable design is reached)
- Document the cores, usage, etc.
There is a dockerfile available with all the required tools!
- nmigen (latest)
- yosys (v0.9+, can use yowasp-yosys)
- cocotb (recommended 1.3.1+)
- icarus verilog
- nmigen-cocotb@icarus-g2005
- pytest, pytest-repeat, pytest-timeout
- numpy
- scipy
python3 -m pytest -vs cnn/ --log-cli-level info