Skip to content

Pull requests: alexforencich/verilog-axi

New pull request New
7 Open 5 Closed
7 Open 5 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

Add explicit python3 prefix to all python paths in test suite
#62 opened Dec 7, 2023 by dbarrie Loading…
Fix AXI_ADDR_BIT_OFFSET and AXIL_ADDR_BIT_OFFSET part select
#49 opened Mar 5, 2023 by AlexLao512 Loading…
6
WIP: Verilator Compatibility
#47 opened Mar 1, 2023 by benreynwar Loading…
add option for initialization file for RAM
#42 opened Dec 18, 2022 by bunnie Loading…
fix numerical overflow in bit shift operation
#41 opened Dec 18, 2022 by bunnie Loading…
Fix readme typo
#27 opened Oct 12, 2021 by FlyGoat Loading…
Updated AXI-lite RAM to pass a formal verification check
#11 opened Nov 6, 2020 by ZipCPU Loading…
1
ProTip! Updated in the last three days: updated:>2024-11-23.