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fix(CMSIS,PeriphDrivers): Add TMR RevB CTRL1.async field which allo…
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…ws asynchronous reads to the PWM and CNT registers (#1294)
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@sihyung-maxim
sihyung-maxim authored Dec 16, 2024
1 parent 4ccce6f commit 0a0bb83
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Showing 23 changed files with 3,778 additions and 3,693 deletions.
6 changes: 6 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd
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Expand Up @@ -11168,6 +11168,12 @@
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNC</name>
<description>Allows asynchronous reads of the PWM and CNT registers.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSEL_B</name>
<description>Timer Clock Select for Timer B</description>
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3 changes: 3 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h
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Expand Up @@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */

#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */

#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */

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6 changes: 6 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd
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Expand Up @@ -10081,6 +10081,12 @@
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNC</name>
<description>Allows asynchronous reads to the PWM and CNT registers.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSEL_B</name>
<description>Timer Clock Select for Timer B</description>
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3 changes: 3 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h
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Expand Up @@ -381,6 +381,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */

#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */

#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */

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6 changes: 6 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd
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Expand Up @@ -8541,6 +8541,12 @@
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNC</name>
<description>Allows asynchronous reads to the PWM and CNT registers.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSEL_B</name>
<description>Timer Clock Select for Timer B</description>
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3 changes: 3 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h
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Expand Up @@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */

#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */

#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */

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6 changes: 6 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd
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Expand Up @@ -11666,6 +11666,12 @@
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNC</name>
<description>Allows asynchronous reads to the PWM and CNT registers.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSEL_B</name>
<description>Timer Clock Select for Timer B</description>
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3 changes: 3 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h
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Expand Up @@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */

#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */

#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */

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6 changes: 6 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd
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Expand Up @@ -8547,6 +8547,12 @@
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNC</name>
<description>Allows asynchronous reads to the PWM and CNT registers.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSEL_B</name>
<description>Timer Clock Select for Timer B</description>
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3 changes: 3 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h
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Expand Up @@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */

#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */

#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */

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6 changes: 6 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd
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Expand Up @@ -19454,6 +19454,12 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNC</name>
<description>Allows asynchronous reads of the PWM and CNT registers.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSEL_B</name>
<description>Timer Clock Select for Timer B</description>
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3 changes: 3 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h
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Expand Up @@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */

#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */

#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */

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6 changes: 6 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd
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Expand Up @@ -11101,6 +11101,12 @@
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNC</name>
<description>Allows asynchronous reads of the PWM and CNT registers.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSEL_B</name>
<description>Timer Clock Select for Timer B</description>
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3 changes: 3 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h
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Expand Up @@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */

#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */

#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */

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6 changes: 6 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd
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Expand Up @@ -16842,6 +16842,12 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASYNC</name>
<description>Allows asynchronous reads of the PWM and CNT registers.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSEL_B</name>
<description>Timer Clock Select for Timer B</description>
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3 changes: 3 additions & 0 deletions Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h
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Expand Up @@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */

#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */

#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */

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