Merge branch stm32_qspi_cr_write into 20204_02_16

drivers/bus/qspi.h

@@ -37,14 +37,20 @@ enum {
     MP_QSPI_IOCTL_DEINIT,
     MP_QSPI_IOCTL_BUS_ACQUIRE,
     MP_QSPI_IOCTL_BUS_RELEASE,
+    MP_QSPI_IOCTL_FLASH_SIZE,
+};
+
+enum qspi_tranfer_mode {
+    MP_QSPI_TRANSFER_CMD_ADDR_DATA,
+    MP_QSPI_TRANSFER_CMD_QADDR_QDATA,
 };
 
 typedef struct _mp_qspi_proto_t {
-    int (*ioctl)(void *self, uint32_t cmd);
+    int (*ioctl)(void *self, uint32_t cmd, uint32_t arg);
     int (*write_cmd_data)(void *self, uint8_t cmd, size_t len, uint32_t data);
     int (*write_cmd_addr_data)(void *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src);
     int (*read_cmd)(void *self, uint8_t cmd, size_t len, uint32_t *dest);
-    int (*read_cmd_qaddr_qdata)(void *self, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest);
+    int (*read_cmd_addr_data)(void *self, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest, uint8_t mode);
 } mp_qspi_proto_t;
 
 typedef struct _mp_soft_qspi_obj_t {

drivers/bus/softqspi.c

@@ -56,7 +56,7 @@ STATIC void nibble_write(mp_soft_qspi_obj_t *self, uint8_t v) {
     mp_hal_pin_write(self->io3, (v >> 3) & 1);
 }
 
-STATIC int mp_soft_qspi_ioctl(void *self_in, uint32_t cmd) {
+STATIC int mp_soft_qspi_ioctl(void *self_in, uint32_t cmd, uint32_t arg) {
     mp_soft_qspi_obj_t *self = (mp_soft_qspi_obj_t*)self_in;
 
     switch (cmd) {
@@ -188,22 +188,34 @@ STATIC int mp_soft_qspi_read_cmd(void *self_in, uint8_t cmd, size_t len, uint32_
     return 0;
 }
 
-STATIC int mp_soft_qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) {
+STATIC int mp_soft_qspi_read_cmd_addr_data(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest, uint8_t mode) {
+    int ret = 0;
     mp_soft_qspi_obj_t *self = (mp_soft_qspi_obj_t*)self_in;
     uint8_t cmd_buf[7] = {cmd};
     uint8_t addr_len = mp_spi_set_addr_buff(&cmd_buf[1], addr);
     CS_LOW(self);
     mp_soft_qspi_transfer(self, 1, cmd_buf, NULL);
-    mp_soft_qspi_qwrite(self, addr_len + 3, &cmd_buf[1]); // 3/4 addr bytes, 1 extra byte (0), 2 dummy bytes (4 dummy cycles)
-    mp_soft_qspi_qread(self, len, dest);
+    if (mode == MP_QSPI_TRANSFER_CMD_ADDR_DATA) {
+        // cmd, address and data on 1 line.
+        // 3 addr bytes, 1 dummy byte (8 dummy cycles x 1 line)
+        mp_soft_qspi_transfer(self, addr_len + 1, &cmd_buf[1], NULL);
+        mp_soft_qspi_transfer(self, len, NULL, dest);
+    } else if (mode == MP_QSPI_TRANSFER_CMD_QADDR_QDATA) {
+        // cmd 1 line, address and data on 4 lines.
+        // 3/4 addr bytes, 1 extra byte (mode: 0), 2 dummy bytes (4 dummy cycles x 4 lines)
+        mp_soft_qspi_qwrite(self, addr_len + 3, &cmd_buf[1]);
+        mp_soft_qspi_qread(self, len, dest);
+    } else {
+        ret = -1;
+    }
     CS_HIGH(self);
-    return 0;
+    return ret;
 }
 
 const mp_qspi_proto_t mp_soft_qspi_proto = {
     .ioctl = mp_soft_qspi_ioctl,
     .write_cmd_data = mp_soft_qspi_write_cmd_data,
     .write_cmd_addr_data = mp_soft_qspi_write_cmd_addr_data,
     .read_cmd = mp_soft_qspi_read_cmd,
-    .read_cmd_qaddr_qdata = mp_soft_qspi_read_cmd_qaddr_qdata,
+    .read_cmd_addr_data = mp_soft_qspi_read_cmd_addr_data,
 };

drivers/memory/external_flash_device.h

@@ -29,11 +29,16 @@
 #include <stdbool.h>
 #include <stdint.h>
 
-typedef struct {
+typedef struct _external_flash_device {
+    // Flash size in bytes.
     uint32_t total_size;
+
     uint16_t start_up_time_us;
 
     // Three response bytes to 0x9f JEDEC ID command.
+    // The first field is always a manufacturer_id, however the other two are used
+    // differently be each manufacturer.
+    // All three together will always uniquely identify a chip model.
     uint8_t manufacturer_id;
     uint8_t memory_type;
     uint8_t capacity;
@@ -66,9 +71,12 @@ typedef struct {
     bool single_status_byte : 1;
 } external_flash_device;
 
-// Settings for the Adesto Tech AT25DF081A 1MiB SPI flash. Its on the SAMD21
-// Xplained board.
+// typedef struct _external_flash_device ;
+
+// Settings for the Adesto Tech / Renesas AT25DF081A 1MiB SPI flash.
+// Its on the SAMD21 Xplained board.
 // Datasheet: https://www.adestotech.com/wp-content/uploads/doc8715.pdf
+//            https://www.renesas.com/eu/en/document/dst/at25df081a-datasheet
 #define AT25DF081A { \
         .total_size = (1 << 20), /* 1 MiB */ \
         .start_up_time_us = 10000, \
@@ -85,6 +93,42 @@ typedef struct {
         .single_status_byte = false, \
 }
 
+// Settings for the Renesas AT25SF161B 2MiB SPI flash.
+// Datasheet: https://www.renesas.com/us/en/document/dst/at25sf161b-datasheet?r=1608796
+#define AT25SF161B { \
+        .total_size = (1 << 21), /* 2 MiB */ \
+        .start_up_time_us = 5000, \
+        .manufacturer_id = 0x1f, \
+        .memory_type = 0x86, \
+        .capacity = 0x01, \
+        .max_clock_speed_mhz = 133, \
+        .quad_enable_bit_mask = 0x02, \
+        .has_sector_protection = true, \
+        .supports_fast_read = true, \
+        .supports_qspi = true, \
+        .supports_qspi_writes = true, \
+        .write_status_register_split = true, \
+        .single_status_byte = false, \
+}
+
+// Settings for the Renesas AT25SF641B 8MiB SPI flash.
+// Datasheet: https://www.renesas.com/us/en/document/dst/at25sf641b-datasheet?r=1608816
+#define AT25SF641B { \
+        .total_size = (1 << 23), /* 8 MiB */ \
+        .start_up_time_us = 5000, \
+        .manufacturer_id = 0x1f, \
+        .memory_type = 0x88, \
+        .capacity = 0x01, \
+        .max_clock_speed_mhz = 133, \
+        .quad_enable_bit_mask = 0x02, \
+        .has_sector_protection = true, \
+        .supports_fast_read = true, \
+        .supports_qspi = true, \
+        .supports_qspi_writes = true, \
+        .write_status_register_split = true, \
+        .single_status_byte = false, \
+}
+
 // Settings for the Gigadevice GD25Q16C 2MiB SPI flash.
 // Datasheet: http://www.gigadevice.com/datasheet/gd25q16c/
 #define GD25Q16C { \
@@ -388,6 +432,24 @@ typedef struct {
         .single_status_byte = true, \
 }
 
+// Settings for the Macronix MX25L25673G 32MiB SPI flash.
+// Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8761/MX25L25673G,%203V,%20256Mb,%20v1.7.pdf
+#define MX25L25673G  { \
+        .total_size = (1 << 25), /* 32 MiB */ \
+        .start_up_time_us = 5000, \
+        .manufacturer_id = 0xc2, \
+        .memory_type = 0x20, \
+        .capacity = 0x19, \
+        .max_clock_speed_mhz = 133, \
+        .quad_enable_bit_mask = 0x40, \
+        .has_sector_protection = false, \
+        .supports_fast_read = true, \
+        .supports_qspi = true, \
+        .supports_qspi_writes = true, \
+        .write_status_register_split = false, \
+        .single_status_byte = true, \
+}
+
 // Settings for the Macronix MX25R6435F 8MiB SPI flash.
 // Datasheet: http://www.macronix.com/Lists/Datasheet/Attachments/7428/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.4.pdf
 // By default its in lower power mode which can only do 8mhz. In high power mode it can do 80mhz.