Synthesis: Add fa/ha extract and techmap pass

This commit adds extra `extract_fa` Yosys pass combined with fa/ha techmapping. It runs only when user specifies $fa/$ha to DPK mapping. This commit also adds new `adder_mapping` attr to the `synthesize_rtl` rule. This file provides Yosys with $fa/$ha blackboxes. This change may affect existing designs, as extra `opt` pass is being run. Signed-off-by: Maciej Dudek <[email protected]>
antmicro · Dec 18, 2023 · 6239bed · 6239bed
1 parent 7a510f1
commit 6239bed
Show file tree

Hide file tree

Showing 2 changed files with 22 additions and 0 deletions.
diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl
@@ -98,6 +98,8 @@ def _synthesize_design_impl(ctx):
     inputs.extend(uhdm_files)
     inputs.append(synth_tcl)
     inputs.append(default_liberty_file)
+    if ctx.attr.adder_mapping:
+        inputs.append(ctx.file.adder_mapping)
 
     (tool_inputs, input_manifests) = ctx.resolve_tools(tools = [ctx.attr.yosys_tool])
 
@@ -130,6 +132,9 @@ def _synthesize_design_impl(ctx):
     if ctx.attr.target_clock_period_pico_seconds:
         script_env_files["CLOCK_PERIOD"] = str(ctx.attr.target_clock_period_pico_seconds)
 
+    if ctx.attr.adder_mapping:
+        script_env_files["ADDER_MAPPING"] = str(ctx.file.adder_mapping.path)
+
     env = {
         "YOSYS_DATDIR": yosys_runfiles_dir + "/at_clifford_yosys/techlibs/",
         "ABC": yosys_runfiles_dir + "/edu_berkeley_abc/abc",
@@ -253,6 +258,10 @@ synthesize_rtl = rule(
             allow_single_file = True,
             doc = "Tcl synthesis script compatible with the environment-variable API of synth.tcl",
         ),
+        "adder_mapping": attr.label(
+            allow_single_file = True,
+            doc = "Verilog file that maps yosys adder to PDK adders."
+        ),
         "target_clock_period_pico_seconds": attr.int(doc = "target clock period in picoseconds"),
         "output_file_name": attr.string(doc = "The output file name."),
     },

diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl
@@ -72,10 +72,23 @@ yosys synth -top $top
 yosys opt_clean -purge
 yosys autoname
 
+# Technology mapping of adders
+if {[info exists ::env(ADDER_MAPPING)] && [file isfile $::env(ADDER_MAPPING)]} {
+  # extract the full adders
+  extract_fa
+  # map full adders
+  techmap -map $::env(ADDER_MAPPING)
+  techmap
+  # Quick optimization
+  opt -fast -purge
+}
+
 # mapping to liberty
 set liberty $::env(LIBERTY)
 dfflibmap -liberty $liberty
 
+opt
+
 if { [info exists ::env(CLOCK_PERIOD) ] } {
   abc -liberty $liberty -dff -g aig -D $::env(CLOCK_PERIOD) {*}$::env(DONT_USE_ARGS)
 } else {