Skip to content

Commit

Permalink
ASAP7: Add fa/ha mapping
Browse files Browse the repository at this point in the history 
This commit adds fa_ha_mapping files to the
ASAP7 R/L/SL PDKs.

Signed-off-by: Maciej Dudek <[email protected]>
  • Loading branch information
@mtdudek
mtdudek committed Dec 20, 2023
1 parent 7c6b657 commit 67f5b43
Show file tree
Hide file tree
Showing 13 changed files with 185 additions and 0 deletions.
3 changes: 3 additions & 0 deletions dependency_support/org_theopenroadproject_asap7_pdk_r1p7/BUILD
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,4 +25,7 @@ exports_files([
"pdn_config_1x.pdn", # FIXME: Where did this come from?
"pdn_config_4x.pdn", # FIXME: Where did this come from?
"asap7.lyt", # Imported from OpenROAD-flow-scripts on 24.07.2023 at 6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8 from: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8/flow/platforms/asap7/KLayout/asap7.lyt
"cell_adders_R.v",
"cell_adders_L.v",
"cell_adders_SL.v",
])
56 changes: 56 additions & 0 deletions dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_L.v
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,56 @@
// File copy form
// OpenRAOD-flow-scripts@dd552435616bcc18fb2dba0b221f682d9e873fb1
// Only works with asap7 L cell library
(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
(* force_downto *)
output [WIDTH-1 : 0] X, Y;

wire [WIDTH-1 : 0] NX, NY;

parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx;

genvar i;
generate for (i = 0; i < WIDTH; i = i + 1) begin
if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
HAxp5_ASAP7_75t_L halfadder_Cconst (
.A(A[i]),
.B(B[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin
HAxp5_ASAP7_75t_L halfadder_Bconst (
.A(A[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
HAxp5_ASAP7_75t_L halfadder_Aconst (
.A(B[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
end
end
else begin
FAx1_ASAP7_75t_L fulladder (
.A(A[i]), .B(B[i]), .CI(C[i]), .CON(NX[i]), .SN(NY[i])
);
end

assign X[i] = ~NX[i];
assign Y[i] = ~NY[i];

end endgenerate

endmodule
56 changes: 56 additions & 0 deletions dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_R.v
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,56 @@
// File copy form
// OpenRAOD-flow-scripts@dd552435616bcc18fb2dba0b221f682d9e873fb1
// Only works with asap7 R cell library
(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
(* force_downto *)
output [WIDTH-1 : 0] X, Y;

wire [WIDTH-1 : 0] NX, NY;

parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx;

genvar i;
generate for (i = 0; i < WIDTH; i = i + 1) begin
if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
HAxp5_ASAP7_75t_R halfadder_Cconst (
.A(A[i]),
.B(B[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin
HAxp5_ASAP7_75t_R halfadder_Bconst (
.A(A[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
HAxp5_ASAP7_75t_R halfadder_Aconst (
.A(B[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
end
end
else begin
FAx1_ASAP7_75t_R fulladder (
.A(A[i]), .B(B[i]), .CI(C[i]), .CON(NX[i]), .SN(NY[i])
);
end

assign X[i] = ~NX[i];
assign Y[i] = ~NY[i];

end endgenerate

endmodule
56 changes: 56 additions & 0 deletions dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cell_adders_SL.v
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,56 @@
// File copy form
// OpenRAOD-flow-scripts@dd552435616bcc18fb2dba0b221f682d9e873fb1
// Only works with asap7 R cell library
(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
(* force_downto *)
output [WIDTH-1 : 0] X, Y;

wire [WIDTH-1 : 0] NX, NY;

parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx;

genvar i;
generate for (i = 0; i < WIDTH; i = i + 1) begin
if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin
HAxp5_ASAP7_75t_SL halfadder_Cconst (
.A(A[i]),
.B(B[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin
HAxp5_ASAP7_75t_SL halfadder_Bconst (
.A(A[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
else begin
HAxp5_ASAP7_75t_SL halfadder_Aconst (
.A(B[i]),
.B(C[i]),
.CON(NX[i]), .SN(NY[i])
);
end
end
end
else begin
FAx1_ASAP7_75t_SL fulladder (
.A(A[i]), .B(B[i]), .CI(C[i]), .CON(NX[i]), .SN(NY[i])
);
end

assign X[i] = ~NX[i];
assign Y[i] = ~NY[i];

end endgenerate

endmodule
4 changes: 4 additions & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel
View file
Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v",
)

# From org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl
Expand Down Expand Up @@ -162,6 +163,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)

# From org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl
Expand Down Expand Up @@ -287,6 +289,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_4x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)

##########################################################################
Expand Down Expand Up @@ -349,6 +352,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v",
)

# From org_theopenroadproject_asap7sc7p5t_27/common.bzl
Expand Down
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -68,4 +68,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v",
)
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -68,4 +68,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -134,6 +134,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_4x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)

##########################################################################
Expand Down
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -68,4 +68,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v",
)
3 changes: 3 additions & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel
View file
Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v",
)

# From org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl
Expand Down Expand Up @@ -160,6 +161,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)

# From org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl
Expand Down Expand Up @@ -218,6 +220,7 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v",
)

# From org_theopenroadproject_asap7sc7p5t_28/common.bzl
Expand Down
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,4 +67,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v",
)
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,4 +67,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v",
)
1 change: 1 addition & 0 deletions dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,4 +67,5 @@ open_road_pdk_configuration(
tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl",
wire_rc_clock_metal_layer = "M5",
wire_rc_signal_metal_layer = "M2",
ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v",
)

0 comments on commit 67f5b43

Please sign in to comment.