targets/common.py: Do not place a false path between eth_tx and eth_r…

…x clock Internal-tag: [#67942] Signed-off-by: Wiktoria Kuna <[email protected]>
antmicro · Nov 18, 2024 · 6efd222 · 6efd222
1 parent a4f1816
commit 6efd222
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/rowhammer_tester/targets/common.py b/rowhammer_tester/targets/common.py
@@ -125,7 +125,8 @@ def add_host_bridge(self):
         eth_tx_clk.attr.add("keep")
         # Period constraint is specified in ns
         self.platform.add_period_constraint(clock_pads.rx, 1e9/phy.rx_clk_freq)
-        self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
+        self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk)
+        self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_tx_clk)
 
     # Common SoC configuration ---------------------------------------------------------------------