Dev msft #196
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Dev msft #196
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RTL Fix * Remove ECC write-back path in mailbox for correctable ECC errors - the corrected data is merely forwarded to the original requester, but left corrupt in SRAM due to expectation it will never be read again Numerous UVM environment fixes * Fix for reset timing at the environment level * Enforce env-level reset ordering requirements for components * Wait to reset scoreboard until noncore rst asserts * Misc sequence fixes to clear pending interrupts * Clobber all pending/active "delay_jobs" on a hard/noncore reset Related work items: #533427, #533785
…sters and failures * Fixes for many nightly regression soc_ifc register failures. * New soc_ifc register and field changes * Coverage updates for directed tests (soc_ifc_tb) NOTE. couple of tests are still failing. As of now, they resemble testbench timing related issues not RTL. Related work items: #532829, #533940
Dev msft 20230825
calebofearth
approved these changes
Aug 28, 2023
Mailbox Handler Sequence fix: * On detecting MBOX_ERROR state, stall and wait for unlock to end handler seq instead of reporting UVM_ERROR Predictor fixes: * Aggregate the results of multiple delay jobs if they all complete on the same clock cycle - to avoid partial transaction updates being sent to scoreboard * Clear the WDT reset flag on noncore rst deassertion RTL: * Also included a fix for #180 - disable RV assertions for synthesis Related work items: #534128, #534231, #534234
fixing veer rdc violations from uc rst to powergood Created a dedicated gated clock for uc that shuts off to cover both uc rst and warm rst. Related work items: #535520
Move UVM APB agent onto cptra_noncore_rst_b domain. Fix a script issue when compiling multiple fw images (for uvmf_caliptra_top) so that correct object dependencies are used to build each image. Reduce the very large delays that may be randomized for the rand_delay sequence, as this adds little value to the testcase and extends timeouts. Fix for FSM check flagging false failures in the soc_mbox_handler sequence for random invalid register access injection. Related work items: #536549
… key test - enhancing mbox sha to behave more like how ROM will do FIPS test, using direct access path to put the KAT into some region of the mailbox - adding a smoke test that zeroizes during kv operation and confirms that dest valid bits are not set - adding zeroize partial key test to L0 regression Related work items: #527027
fixing sha sequence for constraint solver and issue with start address overlapping the existing data Related work items: #539409
Add cycle-accurate prediction of Watchdog timer interrupt assertion (so it isn't interrupted by random reads to the global_intr reg) Use re-randomization instead of manual assignment for start_addr in sha_accel sequence to adhere to all constraints. Related work items: #539423
Dev msft 20230906
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