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Reintegrate main -> dev-goog #270

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b473793
Add test for Mailbox JTAG accesses with clock gating
robertszczepanski Aug 24, 2023
321e7ae
Update on Readme
Sep 8, 2023
bd6d759
SHA 256 final
Sep 8, 2023
514a42e
update on readme
Sep 12, 2023
42de674
Added HMAC
Sep 12, 2023
797dda7
Updated coprights
ludwigatlubis Sep 13, 2023
5ff2cbc
Create Security and Response policy
FerralCoder Sep 28, 2023
fd73b54
Merge pull request #234 from chipsalliance/main
calebofearth Sep 30, 2023
5b2a0b2
Merged PR 124577: Fix WDT NMI prediction
upadhyayulakiran Sep 15, 2023
ecd5319
Merged PR 125379: added message reduction
mojtaba-bisheh Sep 20, 2023
86a41e6
Merged PR 125576: Increase WDT timer timeout value
upadhyayulakiran Sep 22, 2023
3c503cc
Merged PR 125587: KV clear prediction fix, debug x AHB sequence, conv…
upadhyayulakiran Sep 22, 2023
47b4ceb
Merged PR 126129: added failure in signing if generated signature has…
mojtaba-bisheh Sep 26, 2023
121689d
Merged PR 125683: Scan mode dft override and synchronizer removal
Nitsirks Sep 26, 2023
e39cc0b
Merged PR 126213: Check for pending t1 interrupt before changing time…
upadhyayulakiran Sep 26, 2023
a3c29b8
Merged PR 126577: Coverage merge all duts
Nitsirks Sep 29, 2023
2c300e0
Merged PR 126835: Fixing +COVERAGE compiles that broke after coverage…
Nitsirks Sep 29, 2023
e90baa9
Merged PR 127057: added a missing default case to hmac_drbg_interface
mojtaba-bisheh Oct 2, 2023
62cf3ce
Remove MSFT internal collateral files
calebofearth Oct 2, 2023
779dcee
Merge pull request #235 from chipsalliance/dev-msft-20231002
calebofearth Oct 3, 2023
4fb29d2
Merge pull request #236 from chipsalliance/dev-msft
calebofearth Oct 3, 2023
5608dfa
Merge pull request #238 from chipsalliance/main
calebofearth Oct 3, 2023
cd79995
Merge pull request #239 from chipsalliance/dev-goog
calebofearth Oct 3, 2023
098ef07
Merge pull request #233 from chipsalliance/lferraro_PSIRT
pkwidzin-amd Oct 4, 2023
0c837bf
Merge pull request #240 from chipsalliance/dev-integrate
bharatpillilli Oct 4, 2023
f34255e
Merge pull request #241 from chipsalliance/main
calebofearth Oct 5, 2023
4834f1c
Merged PR 127071: UVM validation FW fix - check/clear error interrupt…
calebofearth Oct 2, 2023
e92adc5
Merged PR 127106: Fix rd_data cg instantiation
upadhyayulakiran Oct 3, 2023
bac4890
Merged PR 127097: More fixes to coverage merging
Nitsirks Oct 3, 2023
677aea2
Merged PR 127448: MSFT sync: Manual file-copy from GH dev-integrate t…
calebofearth Oct 5, 2023
9faace5
Merged PR 127773: Adding caliptra top tb directed regression to cover…
Nitsirks Oct 6, 2023
94ae9e9
Merged PR 127232: UVM fix for soc_ifc_rand_test deadlock edge case
calebofearth Oct 6, 2023
5b1a68f
Merged PR 127980: Fixing MBOX spurious double ecc error
Nitsirks Oct 6, 2023
94d1a60
Merged PR 128205: UVM regression fix for multi-agent arb issue, force…
calebofearth Oct 9, 2023
9d106cd
Merged PR 127470: Disable timers after first timeout before NMI check
upadhyayulakiran Oct 10, 2023
3d18311
Merged PR 128247: [UVM] Fixes in val env. for several regression fail…
calebofearth Oct 12, 2023
d7c4dcc
Merged PR 128855: [Bug fix] Mailbox rd_valid_f signal rst/init value;…
calebofearth Oct 13, 2023
822092f
Remove integ spec PDF as we migrate to Markdown format
calebofearth Oct 17, 2023
77a85df
README updates:
calebofearth Oct 17, 2023
396e5b9
Formatting
calebofearth Oct 17, 2023
1be2d3d
Formatting
calebofearth Oct 17, 2023
bb8288d
Formatting
calebofearth Oct 17, 2023
7a22a64
Formatting
calebofearth Oct 17, 2023
1b3e919
Formatting
calebofearth Oct 17, 2023
c54c3ec
README: Tool version info
calebofearth Oct 17, 2023
751abe7
Merge pull request #253 from chipsalliance/dev-goog
calebofearth Oct 20, 2023
3fed8d2
Merge pull request #252 from chipsalliance/dev-msft-20231017
calebofearth Oct 20, 2023
28adde5
Merge pull request #254 from chipsalliance/dev-msft
calebofearth Oct 21, 2023
c77faf0
initial markdown conversion
steph-morton Oct 24, 2023
3d1fb9f
Merge pull request #205 from ludwigatlubis/main
andreslagarcavilla Oct 25, 2023
5eb4852
Merge pull request #197 from antmicro/rszc/jtag-cg-test
andreslagarcavilla Oct 25, 2023
a11b2f3
Merge pull request #255 from chipsalliance/dev-integrate
andreslagarcavilla Oct 25, 2023
7d9703d
minor updates based on feedback
steph-morton Oct 25, 2023
347600a
Merge pull request #258 from chipsalliance/main
calebofearth Oct 26, 2023
e8e5a41
Merge pull request #256 from chipsalliance/stephm-newdoc
andreslagarcavilla Oct 26, 2023
8798526
add images and image references
steph-morton Nov 1, 2023
5c66ed0
Update Caliptra_rtl.md
Nitsirks Nov 1, 2023
f8993b4
Merged PR 129340: KV debug test update and other misc items
upadhyayulakiran Oct 24, 2023
e0f658f
Merged PR 130632: Remove common_defines from clk_gate
upadhyayulakiran Oct 24, 2023
955d03b
Merged PR 130640: Small coverage improvements and adding directed tb …
Nitsirks Oct 24, 2023
31da078
Merged PR 130547: UVM val FW bug fix to resolve regression failure
calebofearth Oct 24, 2023
f7daac8
Merged PR 131583: Regression test list typo fix
calebofearth Oct 30, 2023
c932181
Merged PR 131385: fix for req hold bug, issue 259
Nitsirks Oct 31, 2023
64888d3
Merged PR 131836: Include config_defines in clk_gate
upadhyayulakiran Oct 31, 2023
b6e79dc
Merged PR 131898: RDL register description updates and fix for UVM pr…
calebofearth Nov 1, 2023
4631e4f
Merge pull request #267 from chipsalliance/stephm-addimages
andreslagarcavilla Nov 1, 2023
1448b38
Merge pull request #269 from chipsalliance/dev-msft-20231101
calebofearth Nov 1, 2023
229ff7a
Merge pull request #271 from chipsalliance/dev-msft
calebofearth Nov 2, 2023
d652e01
Merge pull request #268 from chipsalliance/michnorris-msft-issue266
andreslagarcavilla Nov 2, 2023
2f101fb
Camel case for markdown docs
andreslagarcavilla Nov 2, 2023
0e050e9
Merged PR 132089: fixing wait count, worst case is actually 33 for di…
Nitsirks Nov 1, 2023
92c6aea
Merged PR 132153: TB Fix: soc_ifc_tb standalone test is incorrectly c…
calebofearth Nov 2, 2023
b29d967
Merge pull request #272 from andreslagarcavilla/docs
andreslagarcavilla Nov 2, 2023
4130f93
Fix mv path
andreslagarcavilla Nov 2, 2023
a1035bd
Merge pull request #274 from andreslagarcavilla/docs
andreslagarcavilla Nov 2, 2023
ef953f9
Clarify eTRNG usage
andreslagarcavilla Nov 2, 2023
b54911f
Language: RNG -> TRNG
andreslagarcavilla Nov 2, 2023
447bf27
Update integ spec to 0.9 version; rollback release notes to reflect 0…
calebofearth Nov 3, 2023
f86a38d
Language, simplification
andreslagarcavilla Nov 3, 2023
92876e1
Merge pull request #273 from chipsalliance/dev-msft-20231102
calebofearth Nov 3, 2023
452e187
Version docs at 1.0-rc1
calebofearth Nov 3, 2023
9983f6c
Update CaliptraIntegrationSpecification.md
Nitsirks Nov 3, 2023
bc8642f
Merge pull request #277 from chipsalliance/dev-msft
calebofearth Nov 3, 2023
7c3e295
Merge pull request #275 from andreslagarcavilla/docs
andreslagarcavilla Nov 3, 2023
2b21b0d
Update CaliptraIntegrationSpecification.md
Nitsirks Nov 3, 2023
45a095b
RDL: Add RNG unavail bit to dbg manuf reg description (#283)
calebofearth Nov 3, 2023
1af0865
Merge pull request #279 from chipsalliance/michnorris-msft-issue278
andreslagarcavilla Nov 4, 2023
6ed6523
Merge pull request #281 from chipsalliance/dev-integrate
andreslagarcavilla Nov 7, 2023
020d315
Merge pull request #276 from chipsalliance/cwhitehead-msft-issue263
andreslagarcavilla Nov 7, 2023
b0a25ba
Merge pull request #286 from chipsalliance/main
calebofearth Nov 10, 2023
fa5e334
Merged PR 132462: [UVM] Fix for regression failure caused by soc_ifc …
calebofearth Nov 3, 2023
052c39e
Merged PR 133196: KV test content for coverage
upadhyayulakiran Nov 8, 2023
c3b817d
Merged PR 132944: UVM val firmware bug fix: solve a possible error ra…
calebofearth Nov 8, 2023
86d6ecf
Merged PR 133433: Add SV assertions to uvmf_caliptra_top testbench
calebofearth Nov 9, 2023
7c49c8c
Merged PR 133575: Remove top port TODO comments
calebofearth Nov 10, 2023
7a499fa
Spec update with synthesis warnings and jtag tck requirement
Nov 10, 2023
869c44f
Added some more description
Nov 13, 2023
5bbdd26
Apply suggestion from review
Nov 13, 2023
fd928d2
Remove accidentally placed description
Nov 13, 2023
63ad025
Merge pull request #292 from chipsalliance/kupadhyayula-msft-integ-sp…
bharatpillilli Nov 13, 2023
81a774b
Merge pull request #293 from chipsalliance/dev-msft-20231110
calebofearth Nov 13, 2023
1ce9ea6
Update expected mailbox rdptr value
mkurc-ant Nov 14, 2023
f12c8fe
Merge pull request #296 from chipsalliance/dev-msft
calebofearth Nov 14, 2023
4a89cff
Remove I3C interface placeholder comment (#300)
calebofearth Nov 15, 2023
674ac5f
Merge pull request #302 from antmicro/mkurc/fix-mailbox-test
mcockrell-google Nov 16, 2023
986b12a
Remove support for JTAG read IDCODE instruction from VeeR TAP
mkurc-ant Nov 14, 2023
cf4903d
Remove expected IDCODE from OpenOCD config
mkurc-ant Nov 14, 2023
7589fe4
Merge pull request #298 from antmicro/mkurc/remove-idcode
kgugala Nov 21, 2023
0a512a7
initial markdown conversion of hardware spec
steph-morton Nov 21, 2023
eeb0a57
[README] Update VCS steps (#308)
calebofearth Nov 22, 2023
532117f
Merge pull request #309 from chipsalliance/stephm-newdoc
andreslagarcavilla Nov 28, 2023
63a40f0
Fix VCS invocation in Makefile so that DPI functions get compiled. (#…
mkurc-ant Nov 30, 2023
8173b30
Merged PR 133861: Filesystem merge from caliptra-rtl GitHub to MSFT i…
calebofearth Nov 14, 2023
3cc699b
Commit minor tweaks to sync infrastructure with MSFT internal repo (h…
calebofearth Nov 30, 2023
38d5fd7
Merged PR 134395: KV UVM fixes
upadhyayulakiran Nov 15, 2023
a622696
Merged PR 134100: Update synthesis script with FC commands
upadhyayulakiran Nov 15, 2023
340a3cd
Merged PR 134598: UVM regression fixes for soc_ifc deadlock and AHB s…
calebofearth Nov 17, 2023
c5884b8
Merged PR 134981: Update kv scan sequence
upadhyayulakiran Nov 18, 2023
15acd7b
Merged PR 136182: Fix ICCM ECC error not reported
calebofearth Nov 30, 2023
5bdfabd
Merge pull request #318 from chipsalliance/dev-msft-20231130
calebofearth Dec 1, 2023
c1ad07c
Merge pull request #319 from chipsalliance/dev-msft
calebofearth Dec 1, 2023
9082743
Merge pull request #310 from chipsalliance/dev-public
calebofearth Dec 1, 2023
e181daf
Merge pull request #299 from chipsalliance/dev-integrate
andreslagarcavilla Dec 1, 2023
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Added some more description
Kiran Upadhyayula committed Nov 13, 2023
commit 869c44fa1516449d7e40267138efcdd4e8edc8e1
19 changes: 9 additions & 10 deletions docs/CaliptraIntegrationSpecification.md
Original file line number Diff line number Diff line change
@@ -608,9 +608,6 @@ The following table describes SoC integration requirements.
| Deobfuscation Key | Rotation of the deobfuscation key (if not driven through PUF) between silicon steppings of a given product (for example, A0 vs. B0 vs. PRQ stepping) is dependent on company-specific policies. | Statement of conformance | Required by UDS and Field Entropy threat model |
| Deobfuscation Key | SoC backend flows should not insert deobfuscation key flops into the scan chain. | Synthesis report | Required by UDS and Field Entropy threat model |
| Deobfuscation Key | For defense in depth, it is strongly recommended that debofuscation key flops are not on the scan chain. <br> Remove the following signals from the scan chain: <br> cptra_scan_mode_Latched_d <br> cptra_scan_mode_Latched_f <br> field_storage.internal_obf_key | Statement of conformance | Caliptra HW threat model |
| CSR Signing Key | SoC backend flows shall generate CSR signing key with appropriate NIST compliance as dictated in the Caliptra RoT specification. | Statement of conformance | Required by IDevID threat model |
| CSR Signing Key | Rotation of the CSR private key between silicon steppings of a given product (for example, A0 vs. B0 vs. PRQ stepping) is dependent on company-specific policies. | Statement of conformance | |
| CSR Signing Key | SoC backend flows should not insert CSR signing key flops into the scan chain. | Synthesis report | Required by IDevID threat model |
| DFT | Before scan is enabled (separate signal that SoC implements on scan insertion), SoC shall set Caliptra's scan_mode indication to '1 to allow secrets/assets to be flushed. | Statement of conformance | Required by Caliptra threat model |
| DFT | Caliptra’s TAP should be a TAP endpoint. | Statement of conformance | Functional requirement |
| Mailbox | SoC shall provide an access path between the mailbox and the application CPU complex on SoCs with such complexes (for example, Host CPUs and Smart NICs). See the [Sender Protocol](#sender-protocol) section for details about error conditions. | Statement of conformance | Required for Project Kirkland and TDISP TSM |
@@ -653,13 +650,13 @@ The following table describes SoC integration requirements.

*Table 18: Caliptra synthesis warnings for FEV evaluation*

| Module | Warning | Line No. |
| :--------- | :--------- | :--------- |
| sha512_acc_top | Empty netlist for always_comb | 417 |
| ecc_scalar_blinding | Netlist for always_ff block does not contain flip flop | 301 |
| sha512_masked_core | "masked_carry" is read before being assigned. Synthesized result may not match simulation | 295, 312 |
| ecc_montgomerymultiplier | Netlist for always_ff block does not contain flip flop | 274, 326 |
| Multiple modules | Signed to unsigned conversion occurs | |
| Module | Warning | Line No. | Description |
| :--------- | :--------- | :--------- | :--------- |
| sha512_acc_top | Empty netlist for always_comb | 417 |Unused logic (no load)|
| ecc_scalar_blinding | Netlist for always_ff block does not contain flip flop | 301 |Output width is smaller than internal signals, synthesis optimizes away the extra internal flops with no loads|
| sha512_masked_core | "masked_carry" is read before being assigned. Synthesized result may not match simulation | 295, 312 ||
| ecc_montgomerymultiplier | Netlist for always_ff block does not contain flip flop | 274, 326 |Output width is smaller than internal signals, synthesis optimizes away the extra internal flops with no loads|
| Multiple modules | Signed to unsigned conversion occurs | ||

# CDC analysis and constraints

@@ -703,6 +700,8 @@ Synthesis experiments have so far found the following:
* Design converges at 400MHz 0.72V using a cutting edge TSMC process.
* Design converges at 100MHz using TSMC 40nm process.

Note: Any synthesis warnings of logic optimization must be reviewed and accounted for.

# Netlist synthesis data

The following table illustrates representative netlist synthesis results using industry standard EDA synthesis tools and tool configurations.