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Merge dev-msft -> dev-integrate #271
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FV SHA512, SHA25, HMAC - final
Merge dev-integrate -> main
Reintegrate main -> dev-msft
1. KV debug test update to issue reset every time debug/scan mode is toggled 2. Update rst window assertions to disable during scan mode 3. Add common_defines to clk_gate.sv (#248) 4. Add WDT + rst test 5. WDT regression fix Related work items: #574347, #574348
common_defines inclusion in clk_gate.sv causes compilation issues
…to merge pipeline - cleaning up coverage merge pipeline - updating map file for directed testbench mappings - Adding streaming case from caliptra side for sha accelerator to hit stall condition - Removed coverpoints that can't be hit - soc ifc reg doesn't stall, so ip signal isn't valid - Boot done -> idle arc is tied off. State is terminal Related work items: #486758, #563789
Do an FSM check again upon detecting error interrupt - to catch late-asserting error transition Related work items: #575104
Fix a typo in the firmware test list providing testsuite for nightly directed regression Related work items: #582436
fix for req hold bug, issue 259 sha mbox accesses would always assert req_hold the entire time, even if there was no conflict fixed by qualifying the hold correctly, now soc or uc can read mbox registers without getting held Related work items: #579190
Include config_defines in clk_gate Related work items: #583044
…ediction issue Add enhanced text descriptions for all of the error fatal/non-fatal registers and their internal mask registers that explains how the register contents and transitions are related to the assertion of output interrupt signals, cptra_error_fatal and cptra_error_non_fatal. Add text description for CPTRA_DBG_MANUF_SERVICE_REG, which resolves github issue #261 Add a fix in the UVM class soc_ifc_predictor to correct the prediction of cptra_error_non_fatal based on triggering events instead of directly calculating the interrupt pin based on register contents. Related work items: #583195
Dev msft 20231101
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