Build(deps): Bump third_party/yosys from 6f3376c to 889894a
#6084
Triggered via pull request
December 3, 2024 07:49
dependabot[bot]
Status
Failure
Total duration
1h 10m 42s
Artifacts
49
main.yml
on: pull_request
Matrix: build-binaries
Build tools
11m 22s
Emit Workflow Info
0s
Style check
1m 28s
Verify README Correctness (Installation From Sources)
41m 43s
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 21s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 21s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
24m 58s
Large Designs Tests
/
Opentitan (synthesis)
48m 23s
Large Designs Tests
/
VeeR-EH1 (synthesis)
5m 12s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
13m 31s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
34m 57s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) with PySynlig)
30m 27s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 29s
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests
/
Generate AST diff
1m 40s
Parsing Tests
/
Summary Generation
1m 27s
Verify README Correctness (Download And Run Release)
0s
Annotations
1 error and 4 warnings
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Formal Verification Tests / yosys
Process completed with exit code 1.
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build
third_party/OpenROAD-flow-scripts/logs
third_party/OpenROAD-flow-scripts/reports
third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
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Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
binaries-asan
|
292 MB |
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binaries-package
|
23.2 MB |
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binaries-plugin
|
41.7 MB |
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binaries-pysynlig
|
651 MB |
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binaries-release
|
42 MB |
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bp_e_bp_unicore_cfg.edif
|
3.92 MB |
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bsg-logs
|
5.57 MB |
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bsg-outputs
|
1.73 MB |
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formal-verification-logs-simple
|
18.6 MB |
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formal-verification-logs-sv2v
|
62.7 MB |
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formal-verification-logs-yosys
|
50.2 MB |
|
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lowrisc_ibex_top_artya7_surelog_0.1.bit
|
105 KB |
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lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
|
616 KB |
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opentitan-logs-full
|
4.56 MB |
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opentitan-logs-quick
|
829 KB |
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plots_binaries-asan
|
54.2 KB |
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plots_binaries-package
|
150 KB |
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plots_binaries-plugin
|
121 KB |
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plots_binaries-pysynlig
|
148 KB |
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plots_binaries-release
|
150 KB |
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plots_blackparrot_synth_asic
|
213 KB |
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plots_blackparrot_synth_xilinx
|
89.3 KB |
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plots_blackparrot_synth_xilinx_python
|
182 KB |
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plots_build_tools
|
82.8 KB |
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plots_formal_verification_simple
|
116 KB |
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plots_formal_verification_sv2v
|
116 KB |
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plots_formal_verification_yosys
|
98.2 KB |
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plots_ibex_synth
|
45.4 KB |
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plots_ibex_synth_f4pga
|
79.5 KB |
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plots_opentitan_9d82960888_synth
|
145 KB |
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plots_opentitan_parse_report_full
|
80.4 KB |
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plots_opentitan_parse_report_quick
|
35.3 KB |
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plots_opentitan_synth
|
266 KB |
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plots_tests_asan_read_systemverilog
|
226 KB |
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plots_tests_asan_read_uhdm
|
166 KB |
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plots_tests_plugin_read_systemverilog
|
36.6 KB |
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plots_tests_plugin_read_uhdm
|
32.1 KB |
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plots_tests_release_read_systemverilog
|
34.4 KB |
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plots_tests_release_read_uhdm
|
33.5 KB |
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plots_veer_synth
|
36.4 KB |
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python_bp_e_bp_unicore_cfg.edif
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3.92 MB |
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results_parsing_tests_asan_read_systemverilog
Expired
|
1.6 MB |
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results_parsing_tests_asan_read_uhdm
Expired
|
1.81 MB |
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results_parsing_tests_plugin_read_systemverilog
Expired
|
1.53 MB |
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results_parsing_tests_plugin_read_uhdm
Expired
|
1.78 MB |
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results_parsing_tests_release_read_systemverilog
Expired
|
1.48 MB |
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results_parsing_tests_release_read_uhdm
Expired
|
1.73 MB |
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tools
|
39.2 MB |
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top_artya7.bit
|
119 KB |
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