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Mixed computation, binary computation with XOR-based MACs.
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mkskeller committed Dec 23, 2019
1 parent 12773c4 commit 6fa65c3
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Showing 171 changed files with 2,873 additions and 1,116 deletions.
4 changes: 2 additions & 2 deletions BMR/RealGarbleWire.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ void GarbleJob<T>::middle_round(RealProgramParty<T>& party, Protocol& second_pro
{
second_protocol.prepare_mul(party.shared_delta(j),
lambda_uv + lambda_v * alpha + lambda_u * beta
+ T(alpha * beta, me, party.MC->get_alphai())
+ T::constant(alpha * beta, me, party.MC->get_alphai())
+ lambda_w);
}
}
Expand Down Expand Up @@ -131,7 +131,7 @@ void RealGarbleWire<T>::input(party_id_t from, char input)
assert(party.MC != 0);
auto& protocol = party.shared_proc->protocol;
protocol.init_mul(party.shared_proc);
protocol.prepare_mul(mask, T(1, party.P->my_num(), party.mac_key) - mask);
protocol.prepare_mul(mask, T::constant(1, party.P->my_num(), party.mac_key) - mask);
protocol.exchange();
if (party.MC->open(protocol.finalize_mul(), *party.P) != 0)
throw runtime_error("input mask not a bit");
Expand Down
3 changes: 2 additions & 1 deletion BMR/Register.h
Original file line number Diff line number Diff line change
Expand Up @@ -195,6 +195,7 @@ class BlackHole
template <typename T>
BlackHole& operator<<(T) { return *this; }
BlackHole& operator<<(BlackHole& (*__pf)(BlackHole&)) { (void)__pf; return *this; }
void activate(bool) {}
};
inline BlackHole& endl(BlackHole& b) { return b; }
inline BlackHole& flush(BlackHole& b) { return b; }
Expand All @@ -205,7 +206,7 @@ class Phase
typedef NoMemory DynamicMemory;

typedef BlackHole out_type;
static const BlackHole out;
static BlackHole out;

static void check(const int128& value, word share, int128 mac)
{ (void)value; (void)share; (void)mac; }
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7 changes: 7 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -1,5 +1,12 @@
The changelog explains changes pulled through from the private development repository. Bug fixes and small enhancements are committed between releases and not documented here.

## 0.1.4 (Dec 23, 2019)

- Mixed circuit computation with secret sharing
- Binary computation for dishonest majority using secret sharing as in [FKOS15](https://eprint.iacr.org/2015/901)
- Fixed security bug: insufficient OT correlation check in SPDZ2k
- This version breaks bytecode compatibilty.

## 0.1.3 (Nov 21, 2019)

- Python 3
Expand Down
105 changes: 64 additions & 41 deletions Compiler/GC/instructions.py
Original file line number Diff line number Diff line change
Expand Up @@ -28,13 +28,32 @@ class ClearBitsAF(base.RegisterArgFormat):
LDBITS = 0x20a,
ANDS = 0x20b,
TRANS = 0x20c,
XORCI = 0x210,
BITB = 0x20d,
ANDM = 0x20e,
LDMSB = 0x240,
STMSB = 0x241,
LDMSBI = 0x242,
STMSBI = 0x243,
MOVSB = 0x244,
INPUTB = 0x246,
XORCBI = 0x210,
BITDECC = 0x211,
CONVCINT = 0x213,
REVEAL = 0x214,
STMSDCI = 0x215,
INPUTB = 0x216,
LDMCB = 0x217,
STMCB = 0x218,
XORCB = 0x219,
ADDCB = 0x21a,
ADDCBI = 0x21b,
MULCBI = 0x21c,
SHRCBI = 0x21d,
SHLCBI = 0x21e,
PRINTREGSIGNED = 0x220,
PRINTREGB = 0x221,
PRINTREGPLAINB = 0x222,
PRINTFLOATPLAINB = 0x223,
CONDPRINTSTRB = 0x224,
CONVCBIT = 0x230,
)

Expand All @@ -46,12 +65,12 @@ class xorm(base.Instruction):
code = opcodes['XORM']
arg_format = ['int','sbw','sb','cb']

class xorc(base.Instruction):
code = base.opcodes['XORC']
class xorcb(base.Instruction):
code = opcodes['XORCB']
arg_format = ['cbw','cb','cb']

class xorci(base.Instruction):
code = opcodes['XORCI']
class xorcbi(base.Instruction):
code = opcodes['XORCBI']
arg_format = ['cbw','cb','int']

class andrs(base.Instruction):
Expand All @@ -62,16 +81,20 @@ class ands(base.Instruction):
code = opcodes['ANDS']
arg_format = tools.cycle(['int','sbw','sb','sb'])

class addc(base.Instruction):
code = base.opcodes['ADDC']
class andm(base.Instruction):
code = opcodes['ANDM']
arg_format = ['int','sbw','sb','cb']

class addcb(base.Instruction):
code = opcodes['ADDCB']
arg_format = ['cbw','cb','cb']

class addci(base.Instruction):
code = base.opcodes['ADDCI']
class addcbi(base.Instruction):
code = opcodes['ADDCBI']
arg_format = ['cbw','cb','int']

class mulci(base.Instruction):
code = base.opcodes['MULCI']
class mulcbi(base.Instruction):
code = opcodes['MULCBI']
arg_format = ['cbw','cb','int']

class bitdecs(base.VarArgsInstruction):
Expand All @@ -86,44 +109,44 @@ class bitdecc(base.VarArgsInstruction):
code = opcodes['BITDECC']
arg_format = tools.chain(['cb'], itertools.repeat('cbw'))

class shrci(base.Instruction):
code = base.opcodes['SHRCI']
class shrcbi(base.Instruction):
code = opcodes['SHRCBI']
arg_format = ['cbw','cb','int']

class shlci(base.Instruction):
code = base.opcodes['SHLCI']
class shlcbi(base.Instruction):
code = opcodes['SHLCBI']
arg_format = ['cbw','cb','int']

class ldbits(base.Instruction):
code = opcodes['LDBITS']
arg_format = ['sbw','i','i']

class ldms(base.DirectMemoryInstruction, base.ReadMemoryInstruction):
code = base.opcodes['LDMS']
class ldmsb(base.DirectMemoryInstruction, base.ReadMemoryInstruction):
code = opcodes['LDMSB']
arg_format = ['sbw','int']

class stms(base.DirectMemoryWriteInstruction):
code = base.opcodes['STMS']
class stmsb(base.DirectMemoryWriteInstruction):
code = opcodes['STMSB']
arg_format = ['sb','int']
# def __init__(self, *args, **kwargs):
# super(type(self), self).__init__(*args, **kwargs)
# import inspect
# self.caller = [frame[1:] for frame in inspect.stack()[1:]]

class ldmc(base.DirectMemoryInstruction, base.ReadMemoryInstruction):
code = base.opcodes['LDMC']
class ldmcb(base.DirectMemoryInstruction, base.ReadMemoryInstruction):
code = opcodes['LDMCB']
arg_format = ['cbw','int']

class stmc(base.DirectMemoryWriteInstruction):
code = base.opcodes['STMC']
class stmcb(base.DirectMemoryWriteInstruction):
code = opcodes['STMCB']
arg_format = ['cb','int']

class ldmsi(base.ReadMemoryInstruction):
code = base.opcodes['LDMSI']
class ldmsbi(base.ReadMemoryInstruction):
code = opcodes['LDMSBI']
arg_format = ['sbw','ci']

class stmsi(base.WriteMemoryInstruction):
code = base.opcodes['STMSI']
class stmsbi(base.WriteMemoryInstruction):
code = opcodes['STMSBI']
arg_format = ['sb','ci']

class ldmsdi(base.ReadMemoryInstruction):
Expand Down Expand Up @@ -158,8 +181,8 @@ class convcbit(base.Instruction):
code = opcodes['CONVCBIT']
arg_format = ['ciw','cb']

class movs(base.Instruction):
code = base.opcodes['MOVS']
class movsb(base.Instruction):
code = opcodes['MOVSB']
arg_format = ['sbw','sb']

class trans(base.VarArgsInstruction):
Expand All @@ -169,8 +192,8 @@ def __init__(self, *args):
['sb'] * (len(args) - 1 - args[0])
super(trans, self).__init__(*args)

class bit(base.Instruction):
code = base.opcodes['BIT']
class bitb(base.Instruction):
code = opcodes['BITB']
arg_format = ['sbw']

class reveal(base.Instruction):
Expand All @@ -182,28 +205,28 @@ class inputb(base.DoNotEliminateInstruction, base.VarArgsInstruction):
code = opcodes['INPUTB']
arg_format = tools.cycle(['p','int','int','sbw'])

class print_reg(base.IOInstruction):
code = base.opcodes['PRINTREG']
class print_regb(base.IOInstruction):
code = opcodes['PRINTREGB']
arg_format = ['cb','i']
def __init__(self, reg, comment=''):
super(print_reg, self).__init__(reg, self.str_to_int(comment))
super(print_regb, self).__init__(reg, self.str_to_int(comment))

class print_reg_plain(base.IOInstruction):
code = base.opcodes['PRINTREGPLAIN']
class print_reg_plainb(base.IOInstruction):
code = opcodes['PRINTREGPLAINB']
arg_format = ['cb']

class print_reg_signed(base.IOInstruction):
code = opcodes['PRINTREGSIGNED']
arg_format = ['int','cb']

class print_float_plain(base.IOInstruction):
class print_float_plainb(base.IOInstruction):
__slots__ = []
code = base.opcodes['PRINTFLOATPLAIN']
code = opcodes['PRINTFLOATPLAINB']
arg_format = ['cb', 'cb', 'cb', 'cb']

class cond_print_str(base.IOInstruction):
class cond_print_strb(base.IOInstruction):
r""" Print a 4 character string. """
code = base.opcodes['CONDPRINTSTR']
code = opcodes['CONDPRINTSTRB']
arg_format = ['cb', 'int']

def __init__(self, cond, val):
Expand Down
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