Skip to content
View davideschiavone's full-sized avatar

Block or report davideschiavone

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. esl-epfl/x-heep esl-epfl/x-heep Public

    eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

    C 148 81

  2. openhwgroup/cv32e40p openhwgroup/cv32e40p Public

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog 966 423

  3. lowRISC/ibex lowRISC/ibex Public

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog 1.4k 547