Fix syntax error in gpio_control_block (#60)

* Fix syntax error in gpio_control_block Fixed syntax error that was only visible when running iverilog for simulation * Apply automatic changes to Manifest and README.rst Co-authored-by: marwaneltoukhy <[email protected]>
efabless · Apr 9, 2022 · 14142eb · 14142eb
1 parent c84e139
commit 14142eb
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/manifest b/manifest
@@ -13,7 +13,7 @@ d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76  verilog/rtl/chip_io.v
 126aff02aa229dc346301c552d785dec76a4d68e  verilog/rtl/clock_div.v
 36af0303a0e84ce4a40a854ef1481f8a56bc9989  verilog/rtl/digital_pll.v
 ce49f9af199b5f16d2c39c417d58e5890bc7bab2  verilog/rtl/digital_pll_controller.v
-e4740845a6a543b5dcc74f5c356d5542d2e15f31  verilog/rtl/gpio_control_block.v
+41f899d8a8510f933e08e41d1b4ac13d84191f38  verilog/rtl/gpio_control_block.v
 9c92ddf1391fa75ee906e452e168ca2cdd23bd18  verilog/rtl/gpio_defaults_block.v
 32d395d5936632f3c92a0de4867d6dd7cd4af1bb  verilog/rtl/gpio_logic_high.v
 5469b880904d6dd5d1eba6f026b3582810df412c  verilog/rtl/housekeeping.v

diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
@@ -170,7 +170,7 @@ module gpio_control_block #(
             .VNB(vssd),
 `endif
             .X(serial_data_post_1),
-            .A(serial_data_pre),
+            .A(serial_data_pre)
     );
 
     sky130_fd_sc_hd__dlygate4sd2_1 data_delay_2 (
@@ -181,7 +181,7 @@ module gpio_control_block #(
             .VNB(vssd),
 `endif
             .X(serial_data_post_2),
-            .A(serial_data_post_1),
+            .A(serial_data_post_1)
     );
 
     assign serial_data_out = serial_data_post_2 & one;