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Merge pull request #48 from efabless/serial_refactor
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serial_refactor -> develop
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@Manarabdelaty
Manarabdelaty authored Apr 13, 2021
2 parents c37d629 + 4585ebd commit 698cb3c
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8 changes: 4 additions & 4 deletions manifest
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ d328f88dd48e015bbaa95e0d7c88954343cc5632 verilog/rtl/DFFRAM.v
dab57f3c5464ce3354219840dae589a3fcd27135 verilog/rtl/DFFRAMBB.v
5b8f20f73f6edbbd9566cd5145de6f3ad1e9e351 verilog/rtl/__uprj_netlists.v
d375046abc8fddc3cb2edc9343527369ed16b2fd verilog/rtl/__user_project_wrapper.v
fd22f69975ce98ebb0f8329aad97347e4d1e368e verilog/rtl/caravel.v
891155965a645f2de5377f3ef351d6a76a9fbddd verilog/rtl/caravel.v
b2feeb2a098894d5d731a5b011858a471e855d73 verilog/rtl/caravel_clocking.v
2f81d7936062037160cfdad06997cc0b84439511 verilog/rtl/chip_io.v
d772308bd2a72121d7ed9dcdd40c8e6cbbe4b43c verilog/rtl/clock_div.v
Expand All @@ -16,12 +16,12 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
baf3aba29655ca7021398ddc3f68be81eff0fa0c verilog/rtl/housekeeping_spi.v
0544035d9f2bfc52ebcb3220a21f29e98a3784b4 verilog/rtl/la_wb.v
ff3e65a783f3807340e25efac9207787d39fb6cd verilog/rtl/mem_wb.v
65feb79043201d3609307a3dd5af4e75cc26e81b verilog/rtl/mgmt_core.v
9652d14fdb47dbe79f515d2ec3977661e695bc28 verilog/rtl/mgmt_core.v
4d42909e102c472504739bc37559c6a34fd85ae1 verilog/rtl/mgmt_protect.v
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
990e80add8b881f67d70eb52663dd885fddb8f7a verilog/rtl/mgmt_soc.v
ec1f73fb2baf49327da35f94bdce6c6e3f7271ea verilog/rtl/mgmt_soc.v
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
93eb7aa0f8489715145ff0870737fecf8be1fa8c verilog/rtl/mprj_ctrl.v
046df3ae1eae9237e6454ba2e0c1f74f104c6bd7 verilog/rtl/mprj_ctrl.v
4fb62434bf82c8cd7737afcd2a498d2484ffaaf3 verilog/rtl/mprj_io.v
d4dba320b923398939fcc45ed9db8ed61d71dcdf verilog/rtl/mprj_logic_high.v
eac1e6d413cdfbc2f802e229ae5058828e01be1e verilog/rtl/pads.v
Expand Down
124 changes: 88 additions & 36 deletions verilog/rtl/caravel.v
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Original file line number Diff line number Diff line change
Expand Up @@ -104,7 +104,8 @@ module caravel (
// User Project Control (pad-facing)
wire mprj_io_loader_resetn;
wire mprj_io_loader_clock;
wire mprj_io_loader_data;
wire mprj_io_loader_data_1; /* user1 side serial loader */
wire mprj_io_loader_data_2; /* user2 side serial loader */

wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n;
wire [`MPRJ_IO_PADS-1:0] mprj_io_enh;
Expand All @@ -128,7 +129,8 @@ module caravel (
wire [`MPRJ_IO_PADS-8:0] user_analog_io;

/* Padframe control signals */
wire [`MPRJ_IO_PADS-1:0] gpio_serial_link;
wire [`MPRJ_IO_PADS-1:0] gpio_serial_link_1;
wire [`MPRJ_IO_PADS-2:0] gpio_serial_link_2;
wire mgmt_serial_clock;
wire mgmt_serial_resetn;

Expand All @@ -151,8 +153,6 @@ module caravel (
wire jtag_out, sdo_out;
wire jtag_outenb, sdo_outenb;

wire [`MPRJ_IO_PADS-3:0] mgmt_io_nc1; /* no-connects */
wire [`MPRJ_IO_PADS-3:0] mgmt_io_nc3; /* no-connects */
wire [1:0] mgmt_io_nc2; /* no-connects */

wire clock_core;
Expand Down Expand Up @@ -365,7 +365,8 @@ module caravel (
.mprj2_vdd_pwrgood(mprj2_vdd_pwrgood),
.mprj_io_loader_resetn(mprj_io_loader_resetn),
.mprj_io_loader_clock(mprj_io_loader_clock),
.mprj_io_loader_data(mprj_io_loader_data),
.mprj_io_loader_data_1(mprj_io_loader_data_1),
.mprj_io_loader_data_2(mprj_io_loader_data_2),
.mgmt_in_data(mgmt_io_in),
.mgmt_out_data({mgmt_io_in[(`MPRJ_IO_PADS-1):2], mgmt_io_nc2}),
.pwr_ctrl_out(pwr_ctrl_out),
Expand Down Expand Up @@ -493,9 +494,15 @@ module caravel (
/* End user project instantiation */
/*--------------------------------------*/

wire [`MPRJ_IO_PADS-1:0] gpio_serial_link_shifted;
wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1_shifted;
wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2_shifted;

assign gpio_serial_link_shifted = {gpio_serial_link[`MPRJ_IO_PADS-2:0], mprj_io_loader_data};
assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1-2:0],
mprj_io_loader_data_1};
// Note that serial_link_2 is backwards compared to serial_link_1, so it
// shifts in the other direction.
assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2,
gpio_serial_link_2[`MPRJ_IO_PADS_2-1:1]};

// Each control block sits next to an I/O pad in the user area.
// It gets input through a serial chain from the previous control
Expand Down Expand Up @@ -531,8 +538,8 @@ module caravel (
.zero(),

// Serial data chain for pad configuration
.serial_data_in(gpio_serial_link_shifted[1:0]),
.serial_data_out(gpio_serial_link[1:0]),
.serial_data_in(gpio_serial_link_1_shifted[1:0]),
.serial_data_out(gpio_serial_link_1[1:0]),

// User-facing signals
.user_gpio_out(user_io_out[1:0]),
Expand All @@ -554,49 +561,94 @@ module caravel (
.pad_gpio_in(mprj_io_in[1:0])
);

wire [`MPRJ_IO_PADS-1:2] one_loop;
gpio_control_block gpio_control_in [`MPRJ_IO_PADS-1:2] (
wire [`MPRJ_IO_PADS_1-1:2] one_loop1;
gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-1:2] (
`ifdef USE_POWER_PINS
.vccd(vccd),
.vssd(vssd),
.vccd1(vccd1),
.vssd1(vssd1),
.vccd(vccd),
.vssd(vssd),
.vccd1(vccd1),
.vssd1(vssd1),
`endif

// Management Soc-facing signals

.resetn(mprj_io_loader_resetn),
.serial_clock(mprj_io_loader_clock),

.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):2]),
.mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS_1-1):2]),
.mgmt_gpio_oeb(one_loop1),

.one(one_loop1),
.zero(),

// Serial data chain for pad configuration
.serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-1):2]),
.serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-1):2]),

// User-facing signals
.user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-1):2]),
.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-1):2]),
.user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-1):2]),

// Pad-facing signals (Pad GPIOv2)
.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-1):2]),
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-1):2]),
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-1):2]),
.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-1):2]),
.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-1):2]),
.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-1):2]),
.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-1):2]),
.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-1):2]),
.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1*3-1):6]),
.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-1):2]),
.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-1):2]),
.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-1):2])
);

wire [`MPRJ_IO_PADS_2-1:0] one_loop2;
gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-1:0] (
`ifdef USE_POWER_PINS
.vccd(vccd),
.vssd(vssd),
.vccd1(vccd1),
.vssd1(vssd1),
`endif

// Management Soc-facing signals

.resetn(mprj_io_loader_resetn),
.serial_clock(mprj_io_loader_clock),

.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):2]),
.mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-1):2]),
.mgmt_gpio_oeb(one_loop),
.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.mgmt_gpio_oeb(one_loop2),

.one(one_loop),
.one(one_loop2),
.zero(),

// Serial data chain for pad configuration
.serial_data_in(gpio_serial_link_shifted[(`MPRJ_IO_PADS-1):2]),
.serial_data_out(gpio_serial_link[(`MPRJ_IO_PADS-1):2]),
.serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-1):0]),
.serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-1):0]),

// User-facing signals
.user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):2]),
.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):2]),
.user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):2]),
.user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),

// Pad-facing signals (Pad GPIOv2)
.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):2]),
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):2]),
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):2]),
.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):2]),
.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):2]),
.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):2]),
.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):2]),
.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):2]),
.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):6]),
.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):2]),
.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):2]),
.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):2])
.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):(`MPRJ_IO_PADS_1*3)]),
.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)]),
.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS_1)])
);

user_id_programming #(
Expand Down
11 changes: 8 additions & 3 deletions verilog/rtl/defines.v
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Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,13 @@
// Global parameters
`define __GLOBAL_DEFINE_H

`define MPRJ_IO_PADS 38 /* number of user GPIO pads */
`define MPRJ_PWR_PADS 4 /* vdda1, vccd1, vdda2, vccd2 */
`define MPRJ_IO_PADS_1 19 /* number of user GPIO pads on user1 side */
`define MPRJ_IO_PADS_2 19 /* number of user GPIO pads on user2 side */
`define MPRJ_IO_PADS (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2)

`define MPRJ_PWR_PADS_1 2 /* vdda1, vccd1 enable/disable control */
`define MPRJ_PWR_PADS_2 2 /* vdda2, vccd2 enable/disable control */
`define MPRJ_PWR_PADS (`MPRJ_PWR_PADS_1 + `MPRJ_PWR_PADS_2)

// Size of soc_mem_synth

Expand All @@ -45,4 +50,4 @@
`define DM_INIT 3'b110
`define OENB_INIT 1'b1

`endif // __GLOBAL_DEFINE_H
`endif // __GLOBAL_DEFINE_H
6 changes: 4 additions & 2 deletions verilog/rtl/mgmt_core.v
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,8 @@ module mgmt_core (
input mprj2_vdd_pwrgood,
output mprj_io_loader_resetn,
output mprj_io_loader_clock,
output mprj_io_loader_data,
output mprj_io_loader_data_1,
output mprj_io_loader_data_2,
// WB MI A (User project)
input mprj_ack_i,
input [31:0] mprj_dat_i,
Expand Down Expand Up @@ -244,7 +245,8 @@ module mgmt_core (
.mprj2_vdd_pwrgood(mprj2_vdd_pwrgood),
.mprj_io_loader_resetn(mprj_io_loader_resetn),
.mprj_io_loader_clock(mprj_io_loader_clock),
.mprj_io_loader_data(mprj_io_loader_data),
.mprj_io_loader_data_1(mprj_io_loader_data_1),
.mprj_io_loader_data_2(mprj_io_loader_data_2),
// I/O data
.mgmt_in_data(mgmt_in_data),
.mgmt_out_data(mgmt_out_data),
Expand Down
6 changes: 4 additions & 2 deletions verilog/rtl/mgmt_soc.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,8 @@ module mgmt_soc (
input mprj2_vdd_pwrgood,
output mprj_io_loader_resetn,
output mprj_io_loader_clock,
output mprj_io_loader_data,
output mprj_io_loader_data_1,
output mprj_io_loader_data_2,

// User Project pad data (when management SoC controls the pad)
input [`MPRJ_IO_PADS-1:0] mgmt_in_data,
Expand Down Expand Up @@ -730,7 +731,8 @@ module mgmt_soc (

.serial_clock(mprj_io_loader_clock),
.serial_resetn(mprj_io_loader_resetn),
.serial_data_out(mprj_io_loader_data),
.serial_data_out_1(mprj_io_loader_data_1),
.serial_data_out_2(mprj_io_loader_data_2),
.sdo_oenb_state(sdo_oenb_state),
.jtag_oenb_state(jtag_oenb_state),
.mgmt_gpio_out(mgmt_out_pre),
Expand Down
42 changes: 29 additions & 13 deletions verilog/rtl/mprj_ctrl.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,8 @@ module mprj_ctrl_wb #(
// Output is to serial loader
output serial_clock,
output serial_resetn,
output serial_data_out,
output serial_data_out_1,
output serial_data_out_2,

// Pass state of OEB bit on SDO and JTAG back to the core
// so that the function can be overridden for management output
Expand Down Expand Up @@ -80,7 +81,8 @@ module mprj_ctrl_wb #(

.serial_clock(serial_clock),
.serial_resetn(serial_resetn),
.serial_data_out(serial_data_out),
.serial_data_out_1(serial_data_out_1),
.serial_data_out_2(serial_data_out_2),
.sdo_oenb_state(sdo_oenb_state),
.jtag_oenb_state(jtag_oenb_state),
// .mgmt_gpio_io(mgmt_gpio_io)
Expand Down Expand Up @@ -110,7 +112,8 @@ module mprj_ctrl #(

output serial_clock,
output serial_resetn,
output serial_data_out,
output serial_data_out_1,
output serial_data_out_2,
output sdo_oenb_state,
output jtag_oenb_state,
input [`MPRJ_IO_PADS-1:0] mgmt_gpio_in,
Expand Down Expand Up @@ -301,31 +304,41 @@ module mprj_ctrl #(
endgenerate

reg [3:0] xfer_count;
reg [5:0] pad_count;
reg [4:0] pad_count_1;
reg [5:0] pad_count_2;
reg [1:0] xfer_state;
reg serial_clock;
reg serial_resetn;

reg [IO_CTRL_BITS-1:0] serial_data_staging;
reg [IO_CTRL_BITS-1:0] serial_data_staging_1;
reg [IO_CTRL_BITS-1:0] serial_data_staging_2;

wire serial_data_out;
wire serial_data_out_1;
wire serial_data_out_2;

assign serial_data_out = serial_data_staging[IO_CTRL_BITS-1];
assign serial_data_out_1 = serial_data_staging_1[IO_CTRL_BITS-1];
assign serial_data_out_2 = serial_data_staging_2[IO_CTRL_BITS-1];
assign busy = (xfer_state != `IDLE);

always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) begin

xfer_state <= `IDLE;
xfer_count <= 4'd0;
pad_count <= `MPRJ_IO_PADS;
/* NOTE: This assumes that MPRJ_IO_PADS_1 and MPRJ_IO_PADS_2 are
* equal, because they get clocked the same number of cycles by
* the same clock signal. pad_count_2 gates the count for both.
*/
pad_count_1 <= `MPRJ_IO_PADS_1 - 1;
pad_count_2 <= `MPRJ_IO_PADS_1;
serial_resetn <= 1'b0;
serial_clock <= 1'b0;

end else begin

if (xfer_state == `IDLE) begin
pad_count <= `MPRJ_IO_PADS;
pad_count_1 <= `MPRJ_IO_PADS_1 - 1;
pad_count_2 <= `MPRJ_IO_PADS_1;
serial_resetn <= 1'b1;
serial_clock <= 1'b0;
if (xfer_ctrl == 1'b1) begin
Expand All @@ -335,15 +348,17 @@ module mprj_ctrl #(
serial_resetn <= 1'b1;
serial_clock <= 1'b0;
xfer_count <= 6'd0;
pad_count <= pad_count - 1;
pad_count_1 <= pad_count_1 - 1;
pad_count_2 <= pad_count_2 + 1;
xfer_state <= `XBYTE;
serial_data_staging <= io_ctrl[pad_count - 1];
serial_data_staging_1 <= io_ctrl[pad_count_1];
serial_data_staging_2 <= io_ctrl[pad_count_2];
end else if (xfer_state == `XBYTE) begin
serial_resetn <= 1'b1;
serial_clock <= ~serial_clock;
if (serial_clock == 1'b0) begin
if (xfer_count == IO_CTRL_BITS - 1) begin
if (pad_count == 0) begin
if (pad_count_2 == `MPRJ_IO_PADS) begin
xfer_state <= `LOAD;
end else begin
xfer_state <= `START;
Expand All @@ -352,7 +367,8 @@ module mprj_ctrl #(
xfer_count <= xfer_count + 1;
end
end else begin
serial_data_staging <= {serial_data_staging[IO_CTRL_BITS-2:0], 1'b0};
serial_data_staging_1 <= {serial_data_staging_1[IO_CTRL_BITS-2:0], 1'b0};
serial_data_staging_2 <= {serial_data_staging_2[IO_CTRL_BITS-2:0], 1'b0};
end
end else if (xfer_state == `LOAD) begin
xfer_count <= xfer_count + 1;
Expand Down

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