Add ASIC_watch multi-project caravel testbench

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "verilog/rtl/multi_project_harness"]
+	path = verilog/rtl/multi_project_harness
+	url = https://github.com/mattvenn/mpw-multi-project-harness

README.md

@@ -1,28 +1,45 @@
-# CIIC Harness  
+# Multi Project Harness
 
-A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
+* This is a proposal for handling multiple projects in the user project area of the [Caravel harness](https://github.com/efabless/caravel)
+* This is a fork of caravel with https://github.com/mattvenn/mpw-multi-project-harness added to /verilog/rtl/
+* user_project_wrapper is then adjusted to instantiate https://github.com/mattvenn/mpw-multi-project-harness/blob/main/multi_project_harness.v
 
-<p align=”center”>
-<img src="/doc/ciic_harness.png" width="75%" height="75%"> 
-</p>
+![multi project harness](doc/multi-project-harness.png)
 
-## Managment SoC
-The managment SoC runs firmware that can be used to:
-- Configure Mega Project I/O pads
-- Observe and control Mega Project signals (through on-chip logic analyzer probes)
-- Control the Mega Project power supply
+# Sub projects
 
-The memory map of the management SoC can be found [here](verilog/rtl/README)
+See https://github.com/mattvenn/mpw-multi-project-harness/blob/main/.gitmodules
+for the list of currently included projects.
 
-## Mega Project Area
-This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10).  See [the Caravel  premliminary datasheet](doc/caravel_datasheet.pdf) for details.
-The repository contains a [sample mega project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter.  </br>
+# Preparation
 
-<p align=”center”>
-<img src="/doc/counter_32.png" width="50%" height="50%">
-</p>
+See https://github.com/mattvenn/mpw-multi-project-harness for details on adding new projects.
 
-The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
-1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/user_proj_example/io_ports).
-2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/user_proj_example/la_test1).
-3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles:  [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
+# Simulation / Verification.
+
+For formal and cocotb simulation of each module see https://github.com/mattvenn/mpw-multi-project-harness
+
+For caravel system simulation see the tests under verilog/dv/caravel/user_proj_example/
+
+# GDS
+
+See https://github.com/mattvenn/mpw-multi-project-harness/blob/main/docs/hardening.md for details on hardening each module into the main macro.
+This macro's GDS/LEF is then added to openlane/user_project_wrapper
+
+For configuration sees:
+
+* openlane/user_project_wrapper/config.tcl 
+* openlane/user_project_wrapper/interactive.tcl
+
+To generate the final GDS, run this command:
+
+    make user_project_wrapper OPENLANE_IMAGE_NAME=openlane:rc5
+
+# Todo
+
+* when the toolchain is working, generate the GDS and add it to the repo
+* info.yaml : update user_level_netlist field
+* add some logo art
+* test input pins in the system simulation
+* how clean does the DRC result need to be?
+* adapt ws2812 for default 10mhz clock rate or be able to update the timing reg

info.yaml

@@ -1,18 +1,17 @@
 --- 
 project: 
-  description: "A template SoC for Google sponsored Open MPW shuttles for SKY130."
+  description: "Multi project including designs from Matt Venn, Michael Betz & Richard Miller"
   foundry: "SkyWater"
-  git_url: "https://github.com/efabless/caravel.git"
-  organization: "Efabless"
-  organization_url: "http://efabless.com"
-  owner: "Tim Edwards"
+  git_url: "https://github.com/mattvenn/multi-project-harness.git"
+  organization: ""
+  organization_url: ""
+  owner: "Matt Venn"
   process: "SKY130"
-  project_name: "Caravel"
+  project_name: "multi-project-harness"
   tags: 
     - "Open MPW"
-    - "Test Harness"
-  category: "Test Harness"
+  category: "multi project"
   top_level_netlist: "verilog/rtl/caravel.v"
-  user_level_netlist: "verilog/gl/user_project_wrapper.v"
+  user_level_netlist: "verilog/rtl/multi_project_harness/multi_project_harness.v"
   version: "1.00"
   cover_image: "doc/ciic_harness.png"

openlane/user_project_wrapper/config.tcl

@@ -21,10 +21,10 @@ set ::env(VERILOG_FILES) "\
 
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$script_dir/../../verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
+	$script_dir/../../verilog/rtl/multi_project_harness/multi_project_harness.v"
 
 set ::env(EXTRA_LEFS) "\
-	$script_dir/../../lef/user_proj_example.lef"
+	$script_dir/multi_project_harness.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$script_dir/../../gds/user_proj_example.gds"
+	$script_dir/multi_project_harness.gds"

openlane/user_project_wrapper/interactive.tcl

@@ -10,7 +10,7 @@ init_floorplan
 
 place_io_ol
 
-add_macro_placement mprj 1150 1700 N
+add_macro_placement mprj 500 500 N
 
 manual_macro_placement f
 

verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c

@@ -0,0 +1,66 @@
+#include "../../defs.h"
+
+#define PROJECT 5
+#define NB_OUTPUTS 28
+
+#define reg_mprj_oeb0 (*(volatile uint32_t*)0x30000004)
+#define reg_mprj_oeb1 (*(volatile uint32_t*)0x30000008)
+#define reg_mprj_ws2812 (*(volatile uint32_t*)0x30000500)
+/*
+	IO Test:
+		- Configures MPRJ pins
+*/
+
+void main()
+{
+	/*
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	Output: 0000_0110_0000_1111  (0x1809) = GPIO_MODE_MGNT_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 1       |
+
+
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+	*/
+
+    /*
+    Inputs
+    36 - Safe mode
+    37 - 2^15Hz crystal clock
+
+    Outputs
+    8  - 14 segment_hxxx
+    15 - 21 segment_xhxx
+    22 - 28 segment_xxmx
+    29 - 35 segment_xxxm
+    */
+    volatile uint32_t *io = &reg_mprj_io_0;
+    for (int i = 8 ; i < 8+NB_OUTPUTS ; i++) {
+        io[i] = GPIO_MODE_USER_STD_OUTPUT;
+    }
+
+    io[36] = GPIO_MODE_USER_STD_INPUT_NOPULL;
+    io[37] = GPIO_MODE_USER_STD_INPUT_NOPULL;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // change to project
+    reg_mprj_slave = PROJECT;
+
+    reg_mprj_oeb1 = (1 << 4) + (1 << 5); //GPIO 36 and 37 as inputs
+
+    // use logic analyser bit 0 as reset
+    reg_la0_ena  = 0x00000000; // bits 31:0 outputs
+    reg_la0_data = 0x00000001; // reset high is on bit 0
+    reg_la0_data = 0x00000000; // low
+
+}

verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v

@@ -0,0 +1,162 @@
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+
+module ASIC_watch_tb;
+    reg clock;
+    reg RSTB;
+    reg power1, power2;
+    reg power3, power4;
+
+    wire gpio;
+    wire [37:0] mprj_io;
+    // inputs
+    reg clk_32768;
+    reg safemode;
+
+    // outputs
+    wire [6:0] segment_hxxx;
+    wire [6:0] segment_xhxx;
+    wire [6:0] segment_xxhx;
+    wire [6:0] segment_xxxh;
+
+    assign segment_hxxx[0] = uut.gpio_control_in[8].pad_gpio_out;
+    assign segment_hxxx[1] = uut.gpio_control_in[9].pad_gpio_out;
+    assign segment_hxxx[2] = uut.gpio_control_in[10].pad_gpio_out;
+    assign segment_hxxx[3] = uut.gpio_control_in[11].pad_gpio_out;
+    assign segment_hxxx[4] = uut.gpio_control_in[12].pad_gpio_out;
+    assign segment_hxxx[5] = uut.gpio_control_in[13].pad_gpio_out;
+    assign segment_hxxx[6] = uut.gpio_control_in[14].pad_gpio_out;
+
+    assign segment_xhxx[0] = uut.gpio_control_in[15].pad_gpio_out;
+    assign segment_xhxx[1] = uut.gpio_control_in[16].pad_gpio_out;
+    assign segment_xhxx[2] = uut.gpio_control_in[17].pad_gpio_out;
+    assign segment_xhxx[3] = uut.gpio_control_in[18].pad_gpio_out;
+    assign segment_xhxx[4] = uut.gpio_control_in[19].pad_gpio_out;
+    assign segment_xhxx[5] = uut.gpio_control_in[20].pad_gpio_out;
+    assign segment_xhxx[6] = uut.gpio_control_in[21].pad_gpio_out;
+
+    assign segment_xxhx[0] = uut.gpio_control_in[22].pad_gpio_out;
+    assign segment_xxhx[1] = uut.gpio_control_in[23].pad_gpio_out;
+    assign segment_xxhx[2] = uut.gpio_control_in[24].pad_gpio_out;
+    assign segment_xxhx[3] = uut.gpio_control_in[25].pad_gpio_out;
+    assign segment_xxhx[4] = uut.gpio_control_in[26].pad_gpio_out;
+    assign segment_xxhx[5] = uut.gpio_control_in[27].pad_gpio_out;
+    assign segment_xxhx[6] = uut.gpio_control_in[28].pad_gpio_out;
+
+    assign segment_xxxh[0] = uut.gpio_control_in[29].pad_gpio_out;
+    assign segment_xxxh[1] = uut.gpio_control_in[30].pad_gpio_out;
+    assign segment_xxxh[2] = uut.gpio_control_in[31].pad_gpio_out;
+    assign segment_xxxh[3] = uut.gpio_control_in[32].pad_gpio_out;
+    assign segment_xxxh[4] = uut.gpio_control_in[33].pad_gpio_out;
+    assign segment_xxxh[5] = uut.gpio_control_in[34].pad_gpio_out;
+    assign segment_xxxh[6] = uut.gpio_control_in[35].pad_gpio_out;
+
+    assign mprj_io[36] = safemode ;
+    assign mprj_io[37] = clk_32768;
+
+    // External clock is used by default.  Make this artificially fast for the
+    // simulation.  Normally this would be a slow clock and the digital PLL
+    // would be the fast clock.
+
+    always #12.5 clock <= (clock === 1'b0);
+    always #12.5 clk_32768 <= (clk_32768 === 1'b0);
+
+    initial begin
+        clock = 0;
+        clk_32768 = 0;
+        safemode = 0;
+    end
+
+
+    initial begin
+        $dumpfile("ASIC_watch.vcd");
+        $dumpvars(0, ASIC_watch_tb);
+
+        // Repeat cycles of 1000 clock edges as needed to complete testbench
+        repeat (15) begin
+            repeat (1000) @(posedge clock);
+            // $display("+1000 cycles");
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    initial begin
+        RSTB <= 1'b0;
+        #2000;
+        RSTB <= 1'b1;       // Release reset
+    end
+
+    initial begin       // Power-up sequence
+        power1 <= 1'b0;
+        power2 <= 1'b0;
+        power3 <= 1'b0;
+        power4 <= 1'b0;
+        #200;
+        power1 <= 1'b1;
+        #200;
+        power2 <= 1'b1;
+        #200;
+        power3 <= 1'b1;
+        #200;
+        power4 <= 1'b1;
+    end
+
+    wire flash_csb;
+    wire flash_clk;
+    wire flash_io0;
+    wire flash_io1;
+
+    wire VDD1V8;
+    wire VDD3V3;
+    wire VSS;
+
+    assign VDD3V3 = power1;
+    assign VDD1V8 = power2;
+    wire USER_VDD3V3 = power3;
+    wire USER_VDD1V8 = power4;
+    assign VSS = 1'b0;
+
+    caravel uut (
+        .vddio    (VDD3V3),
+        .vssio    (VSS),
+        .vdda     (VDD3V3),
+        .vssa     (VSS),
+        .vccd     (VDD1V8),
+        .vssd     (VSS),
+        .vdda1    (USER_VDD3V3),
+        .vdda2    (USER_VDD3V3),
+        .vssa1    (VSS),
+        .vssa2    (VSS),
+        .vccd1    (USER_VDD1V8),
+        .vccd2    (USER_VDD1V8),
+        .vssd1    (VSS),
+        .vssd2    (VSS),
+        .clock    (clock),
+        .gpio     (gpio),
+        .mprj_io  (mprj_io),
+        .flash_csb(flash_csb),
+        .flash_clk(flash_clk),
+        .flash_io0(flash_io0),
+        .flash_io1(flash_io1),
+        .resetb   (RSTB)
+    );
+
+    spiflash #(
+        .FILENAME("ASIC_watch.hex")
+    ) spiflash (
+        .csb(flash_csb),
+        .clk(flash_clk),
+        .io0(flash_io0),
+        .io1(flash_io1),
+        .io2(),         // not used
+        .io3()          // not used
+    );
+
+endmodule

verilog/dv/caravel/user_proj_example/ASIC_watch/Makefile

@@ -0,0 +1,42 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+#MP_PATH = ../../../../rtl/multi_project_harness
+BEHAVIOURAL_MODELS = ../../ 
+
+TOOLCHAIN_PREFIX?=/opt/riscv32ic/bin/riscv32-unknown-elf-
+PDK_PATH?=/home/bscuser/hacking/skywater-pdk
+
+.SUFFIXES:
+
+PATTERN = ASIC_watch
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	$(TOOLCHAIN_PREFIX)gcc -mabi=ilp32 -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	$(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	$(TOOLCHAIN_PREFIX)objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all