Modified the instrumentation amplifier input stage layout to

avoid implying a pwell around the perimeter where there is nwell
in the top level.  This appears to be an extraction issue in
magic and needs to be investigated, especially as the behavior
is dependent on "extract all" vs. "extract no all", implying that
the setting itself causes some important step to be missed.
However, the layout change, which does not affect the mask-level
layout, allows the faster "extract no all" to be run without
causing an LVS error.

lvs/netgen.log

@@ -1,4 +1,4 @@
-Netgen 1.5.273 compiled on Sat Oct 19 17:04:39 EDT 2024
+Netgen 1.5.273 compiled on Thu Nov 14 20:49:03 EST 2024
 Warning: netgen command 'format' use fully-qualified name '::netgen::format'
 Warning: netgen command 'global' use fully-qualified name '::netgen::global'
 Call to undefined subcircuit sky130_fd_pr__nfet_g5v0d10v5
@@ -70,7 +70,7 @@ Creating placeholder cell definition.
 Call to undefined subcircuit sky130_fd_pr__res_high_po_0p69
 Creating placeholder cell definition.
 
-Reading setup file /usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
+Reading setup file /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
 
 No property w found for device r
 No property l found for device r
@@ -355,7 +355,7 @@ Circuit 1 contains 15 nets,    Circuit 2 contains 12 nets. *** MISMATCH ***
   Flattening non-matched subcircuits sky130_fd_sc_hvl__lsbuflv2hv_1 sky130_fd_sc_hvl__lsbuflv2hv_1
 
 Flattening instances of sky130_fd_sc_hvl__lsbuflv2hv_1 in file ../netlist/layout/sky130_pa_ip__instramp.spice
-Flattening instances of sky130_fd_sc_hvl__lsbuflv2hv_1 in file ../netlist/schematic/sky130_pa_ip__instramp.spice
+Flattening instances of sky130_fd_sc_hvl__lsbuflv2hv_1 in file /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
 
 Contents of circuit 1:  Circuit: 'sky130_fd_sc_hvl__inv_1'
 Circuit sky130_fd_sc_hvl__inv_1 contains 2 device instances.
@@ -569,7 +569,7 @@ Circuit 1 contains 12 nets,    Circuit 2 contains 12 nets.
   Flattening non-matched subcircuits x1_x32_OA x1_x32_OA
 
 Flattening instances of x1_x32_OA in file ../netlist/layout/sky130_pa_ip__instramp.spice
-Flattening instances of x1_x32_OA in file ../netlist/schematic/sky130_pa_ip__instramp.spice
+Flattening instances of x1_x32_OA in file /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
 
 Contents of circuit 1:  Circuit: 'Output_OA'
 Circuit Output_OA contains 302 device instances.
@@ -646,7 +646,7 @@ Circuit 1 contains 12 nets,    Circuit 2 contains 12 nets.
   Flattening non-matched subcircuits Output_OA Output_OA
 
 Flattening instances of Output_OA in file ../netlist/layout/sky130_pa_ip__instramp.spice
-Flattening instances of Output_OA in file ../netlist/schematic/sky130_pa_ip__instramp.spice
+Flattening instances of Output_OA in file /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
 
 Contents of circuit 1:  Circuit: 'Input_Stage_OA1'
 Circuit Input_Stage_OA1 contains 112 device instances.
@@ -723,7 +723,7 @@ Circuit 1 contains 12 nets,    Circuit 2 contains 12 nets.
   Flattening non-matched subcircuits Input_Stage_OA1 Input_Stage_OA1
 
 Flattening instances of Input_Stage_OA1 in file ../netlist/layout/sky130_pa_ip__instramp.spice
-Flattening instances of Input_Stage_OA1 in file ../netlist/schematic/sky130_pa_ip__instramp.spice
+Flattening instances of Input_Stage_OA1 in file /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
 
 Contents of circuit 1:  Circuit: 'Input_Stage_OA2'
 Circuit Input_Stage_OA2 contains 202 device instances.
@@ -800,7 +800,7 @@ Circuit 1 contains 12 nets,    Circuit 2 contains 12 nets.
   Flattening non-matched subcircuits Input_Stage_OA2 Input_Stage_OA2
 
 Flattening instances of Input_Stage_OA2 in file ../netlist/layout/sky130_pa_ip__instramp.spice
-Flattening instances of Input_Stage_OA2 in file ../netlist/schematic/sky130_pa_ip__instramp.spice
+Flattening instances of Input_Stage_OA2 in file /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
 
 Contents of circuit 1:  Circuit: 'Parallel_10B_Block2'
 Circuit Parallel_10B_Block2 contains 265 device instances.
@@ -889,7 +889,7 @@ Circuit 1 contains 51 nets,    Circuit 2 contains 51 nets.
   Flattening non-matched subcircuits Parallel_10B_Block2 Parallel_10B_Block2
 
 Flattening instances of Parallel_10B_Block2 in file ../netlist/layout/sky130_pa_ip__instramp.spice
-Flattening instances of Parallel_10B_Block2 in file ../netlist/schematic/sky130_pa_ip__instramp.spice
+Flattening instances of Parallel_10B_Block2 in file /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
 
 Contents of circuit 1:  Circuit: 'Input_Stage_v1'
 Circuit Input_Stage_v1 contains 165 device instances.
@@ -972,7 +972,7 @@ Circuit 1 contains 29 nets,    Circuit 2 contains 29 nets.
   Flattening non-matched subcircuits Input_Stage_v1 Input_Stage_v1
 
 Flattening instances of Input_Stage_v1 in file ../netlist/layout/sky130_pa_ip__instramp.spice
-Flattening instances of Input_Stage_v1 in file ../netlist/schematic/sky130_pa_ip__instramp.spice
+Flattening instances of Input_Stage_v1 in file /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
 
 Contents of circuit 1:  Circuit: 'vbias_gen_pga'
 Circuit vbias_gen_pga contains 2 device instances.

mag/Input_Stage_v1.mag

@@ -1,14 +1,21 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1730992408
+timestamp 1731773078
+<< error_s >>
+rect 14128 -14742 15028 -13842
+rect 14128 -24490 15028 -23590
+rect 14128 -34210 15028 -33310
 << dnwell >>
 rect 14128 -7904 19768 -7862
 rect 22482 -7904 29106 -7862
 rect 14128 -35804 29106 -7904
-rect 14128 -36806 29108 -35804
-rect 14132 -36862 29108 -36806
-rect 14132 -36866 21822 -36862
+rect 14128 -36862 29108 -35804
+rect 14128 -36866 21822 -36862
+<< nwell >>
+rect 14128 -17386 14796 -14742
+rect 14128 -27134 14796 -24490
+rect 14128 -36854 14796 -34210
 << locali >>
 rect 14880 -8006 19731 -7992
 rect 14880 -8042 14988 -8006

mag/run_extract_lay.sh

@@ -5,6 +5,7 @@ load sky130_pa_ip__instramp
 select top cell
 extract path extfiles
 extract unique
+extract no all
 extract all
 ext2spice lvs
 ext2spice short resistor

mag/sky130_pa_ip__instramp.mag

@@ -1,29 +1,25 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1731190381
+timestamp 1731773078
 << dnwell >>
 rect 84 80 29486 37640
 << nwell >>
 rect 4 37432 29566 37720
 rect 4 33252 290 37432
 rect 29280 33252 29566 37432
 rect 4 24578 348 33252
-rect 4 23504 290 24578
-rect 14606 24082 14960 26726
 rect 29218 24578 29566 33252
+rect 4 23504 290 24578
 rect 29280 23532 29566 24578
 rect 4 14830 356 23504
-rect 4 13784 290 14830
-rect 14614 14384 14962 17006
 rect 29220 14858 29566 23532
+rect 4 13784 290 14830
 rect 29278 14434 29566 14858
-rect 14612 14334 14962 14384
 rect 29280 13784 29566 14434
 rect 4 5110 356 13784
-rect 4 308 290 5110
-rect 14614 4614 14964 7258
 rect 29222 5110 29566 13784
+rect 4 308 290 5110
 rect 29278 4686 29566 5110
 rect 29280 308 29566 4686
 rect 4 0 29566 308
@@ -352,7 +348,7 @@ timestamp 1731187918
 transform -1 0 29706 0 1 11584
 box 364 -11384 29434 28258
 use Input_Stage_v1  x2
-timestamp 1730992408
+timestamp 1731773078
 transform -1 0 29402 0 1 41468
 box 14128 -37044 29148 -7862
 use vbias_gen_pga  x3

netlist/layout/sky130_pa_ip__instramp.spice

@@ -58,7 +58,7 @@ XXM1 LOWER AVSS UPPER NGATE sky130_fd_pr__nfet_g5v0d10v5_92HZNS
 XXM2 PGATE LOWER AVDD UPPER sky130_fd_pr__pfet_g5v0d10v5_TUFYNQ
 .ends
 
-.subckt Universal_R_2R_Block2 VD DVDD CMOUT R2RIN R2ROUT VIRTOUT AVSS DVSS AVDD
+.subckt Universal_R_2R_Block2 VD DVDD VIRTOUT CMOUT R2RIN R2ROUT AVSS DVSS AVDD
 Xx1 VD DVDD DVSS DVSS AVDD AVDD VDbuf AVDD DVSS DVSS sky130_fd_sc_hvl__lsbuflv2hv_1
 Xx2 VDbuf DVSS DVSS AVDD AVDD VDBAR sky130_fd_sc_hvl__inv_1
 Xsky130_fd_pr__res_xhigh_po_0p35_Q2LWZP_0 m1_4390_n2466# m1_6792_n1970# m1_4394_n2136#
@@ -941,19 +941,19 @@ X30 a_1542_1984# a_1542_n2416# a_n2738_n2546# sky130_fd_pr__res_xhigh_po_0p35 l=
 X31 a_1708_1984# a_1708_n2416# a_n2738_n2546# sky130_fd_pr__res_xhigh_po_0p35 l=20
 .ends
 
-.subckt Parallel_10B_Block2 V6 V5 V8 V9 V7 VO1 VOUT V4 V3 V2 V0 VCM w_8036_n6718#
-+ VBIAS V1 w_8040_12750# w_3572_3030# w_3570_n6718# w_8038_3030# w_3574_12750# w_7054_n6718#
-+ w_7056_3030# DVDD DVSS AVSS AVDD w_7058_12750#
-Xx1 V8 DVDD VCM x1/R2RIN x13/R2RIN x7/VINN AVSS DVSS AVDD Universal_R_2R_Block2
-Xx2 V5 DVDD VCM x6/VOUT x5/R2RIN x7/VINN AVSS DVSS AVDD Universal_R_2R_Block2
-Xx3 V2 DVDD VCM x3/R2RIN x3/R2ROUT x7/VINN AVSS DVSS AVDD Universal_R_2R_Block2
-Xx4 V0 DVDD VCM x8/VOUT x4/R2ROUT x7/VINN AVSS DVSS AVDD Universal_R_2R_Block2
-Xx5 V6 DVDD VCM x5/R2RIN x5/R2ROUT x7/VINN AVSS DVSS AVDD Universal_R_2R_Block2
+.subckt Parallel_10B_Block2 V6 V5 V8 V9 V7 VO1 VOUT V4 V3 V2 V1 V0 VCM w_8036_n6718#
++ VBIAS w_8040_12750# w_3572_3030# w_3570_n6718# w_8038_3030# w_3574_12750# DVDD w_7054_n6718#
++ w_7056_3030# DVSS AVSS AVDD w_7058_12750#
+Xx1 V8 DVDD x7/VINN VCM x1/R2RIN x13/R2RIN AVSS DVSS AVDD Universal_R_2R_Block2
+Xx2 V5 DVDD x7/VINN VCM x6/VOUT x5/R2RIN AVSS DVSS AVDD Universal_R_2R_Block2
+Xx3 V2 DVDD x7/VINN VCM x3/R2RIN x3/R2ROUT AVSS DVSS AVDD Universal_R_2R_Block2
+Xx4 V0 DVDD x7/VINN VCM x8/VOUT x4/R2ROUT AVSS DVSS AVDD Universal_R_2R_Block2
+Xx5 V6 DVDD x7/VINN VCM x5/R2RIN x5/R2ROUT AVSS DVSS AVDD Universal_R_2R_Block2
 Xx6 AVDD x6/VOUT x6/VINN VCM VBIAS w_3574_12750# w_7058_12750# AVSS w_8040_12750#
 + x1_x32_OA
 Xx7 AVDD VOUT x7/VINN VCM VBIAS w_3570_n6718# w_7054_n6718# AVSS w_8036_n6718# Output_OA
 Xx8 AVDD x8/VOUT x8/VINN VCM VBIAS w_3572_3030# w_7056_3030# AVSS w_8038_3030# x1_x32_OA
-Xx9 V4 DVDD VCM x9/R2RIN x9/R2ROUT x7/VINN AVSS DVSS AVDD Universal_R_2R_Block2
+Xx9 V4 DVDD x7/VINN VCM x9/R2RIN x9/R2ROUT AVSS DVSS AVDD Universal_R_2R_Block2
 Xsky130_fd_pr__res_xhigh_po_0p35_Q2LWZP_0 m1_13604_18506# VCM m1_13272_18506# m1_12290_20904#
 + AVSS m1_12940_18506# m1_13272_18506# m1_13438_20902# x13/R2ROUT m1_13604_18506#
 + m1_13438_20902# x6/VOUT m1_12940_18506# sky130_fd_pr__res_xhigh_po_0p35_Q2LWZP
@@ -963,10 +963,10 @@ Xsky130_fd_pr__res_xhigh_po_0p35_Q2LWZP_1 m1_10646_18508# m1_10146_20906# m1_103
 Xsky130_fd_pr__res_xhigh_po_0p35_Q2LWZP_2 m1_12122_18506# m1_11626_20906# m1_11790_18506#
 + VO1 AVSS m1_11458_18506# m1_11790_18506# x6/VINN m1_12290_20904# m1_12122_18506#
 + x6/VINN m1_11626_20906# m1_11458_18506# sky130_fd_pr__res_xhigh_po_0p35_Q2LWZP
-Xx10 V3 DVDD VCM x3/R2ROUT x9/R2RIN x7/VINN AVSS DVSS AVDD Universal_R_2R_Block2
-Xx11 V1 DVDD VCM x4/R2ROUT x3/R2RIN x7/VINN AVSS DVSS AVDD Universal_R_2R_Block2
-Xx12 V7 DVDD VCM x5/R2ROUT x1/R2RIN x7/VINN AVSS DVSS AVDD Universal_R_2R_Block2
-Xx13 V9 DVDD VCM x13/R2RIN x13/R2ROUT x7/VINN AVSS DVSS AVDD Universal_R_2R_Block2
+Xx10 V3 DVDD x7/VINN VCM x3/R2ROUT x9/R2RIN AVSS DVSS AVDD Universal_R_2R_Block2
+Xx11 V1 DVDD x7/VINN VCM x4/R2ROUT x3/R2RIN AVSS DVSS AVDD Universal_R_2R_Block2
+Xx12 V7 DVDD x7/VINN VCM x5/R2ROUT x1/R2RIN AVSS DVSS AVDD Universal_R_2R_Block2
+Xx13 V9 DVDD x7/VINN VCM x13/R2RIN x13/R2ROUT AVSS DVSS AVDD Universal_R_2R_Block2
 Xsky130_fd_pr__res_xhigh_po_0p35_V6AMGK_0 m1_13942_n11110# m1_23902_n11110# m1_28384_n7734#
 + m1_16266_n11110# m1_17594_n11110# m1_20084_n7734# m1_26226_n11110# m1_23072_n7734#
 + m1_21578_n11110# m1_1824_n7734# m1_15270_n11110# m1_3982_n11110# m1_11452_n7734#
@@ -1427,7 +1427,7 @@ X27 a_n2110_1964# a_n2110_n2396# a_n2406_n2526# sky130_fd_pr__res_xhigh_po_0p35
 
 .subckt Input_Stage_v1 VINP VOUT1 VINN CM VBIAS w_18276_n26882# w_22762_n17134# w_21780_n17134#
 + w_21772_n36602# w_22754_n36602# w_18284_n17134# w_21772_n26882# w_22754_n26882#
-+ w_18276_n36602# AVSS AVDD
++ w_18276_n36602# AVDD AVSS
 Xx1 AVDD x1/VOUT x1/VOUT VINN VBIAS w_22754_n36602# w_21772_n36602# AVSS w_18276_n36602#
 + Input_Stage_OA1
 Xx2 AVDD x2/VOUT x2/VOUT VINP VBIAS w_22754_n26882# w_21772_n26882# AVSS w_18276_n26882#
@@ -1501,11 +1501,11 @@ R0 IBIAS VBIAS sky130_fd_pr__res_generic_m1 w=1 l=0.08
 
 .subckt sky130_pa_ip__instramp V[9] V[8] V[7] V[6] V[5] V[4] V[3] V[2] V[1] V[0] VCM
 + IBIAS AVDD VINP DVDD VOUT AVSS DVSS VINN
-Xx1 V[6] V[5] V[8] V[9] V[7] x1/VO1 VOUT V[4] V[3] V[2] V[0] VCM w_18452_4866# x3/VBIAS
-+ V[1] w_18448_24334# w_22928_14614# w_22930_4866# w_18450_14614# w_22926_24334# w_21948_4866#
-+ w_21946_14614# DVDD DVSS AVSS AVDD w_21944_24334# Parallel_10B_Block2
+Xx1 V[6] V[5] V[8] V[9] V[7] x1/VO1 VOUT V[4] V[3] V[2] V[1] V[0] VCM w_18452_4866#
++ x3/VBIAS w_18448_24334# w_22928_14614# w_22930_4866# w_18450_14614# w_22926_24334#
++ DVDD w_21948_4866# w_21946_14614# DVSS AVSS AVDD w_21944_24334# Parallel_10B_Block2
 Xx2 VINP x1/VO1 VINN VCM x3/VBIAS w_7908_14586# w_3434_24334# w_6918_24334# w_6926_4866#
-+ w_3442_4866# w_7900_24334# w_6926_14586# w_3442_14586# w_7908_4866# AVSS AVDD Input_Stage_v1
++ w_3442_4866# w_7900_24334# w_6926_14586# w_3442_14586# w_7908_4866# AVDD AVSS Input_Stage_v1
 Xx3 x3/VBIAS IBIAS AVSS vbias_gen_pga
 .ends